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2016-06-0008

PT0555-3

08/04/16

13

PI4IOE5V9675

Preliminary Datasheet

16-bit I

Power-on reset

When power is applied to VCC, an internal Power-On Reset (POR) holds the PI4IOE5V9675 in a reset condition until VCC

has reached VPOR. At that point, the reset condition is released and the PI4IOE5V9675 registers and I

machine will initialize to their default states. Thereafter VCC must be lowered below 0.2 V to reset the device.

Interrupt output (INT)

The PI4IOE5V9675 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller.

This gives these chips a kind of master function which can initiate an action elsewhere in the system.

The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device

which has generated the interrupt.

In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling

edge of the write to port pulse the interrupt is definitely deactivated (HIGH).

The interrupt is reset in the read mode on the rising edge of the read from port pulse.

During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset

any change in I/Os will be detected and transmitted as an INT.

Figure 10.Bidirectional I/O expander application

Bidirectional I/O expander applications

In the 8-bit I/O expander application shown in Figure 11, P00 and P01 are inputs, and P02 to P07 are outputs. When used in

this configuration, during a write, the input (P00 and P01) must be written as HIGH so the external devices fully control the input

ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to P07). During a read, the logic

levels of the external devices driving the input ports (P00 and P01) and the previous written logic level to the output ports (P02 to

P07) will be read.The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor. By

sending an interrupt signal on this line, the remote I/O informs the microprocessor that there is incoming data or a change of data

on its ports without having to communicate via the I