UVLO

VIN

RCLASS

FAUX

DCCL

VEE

RAUX

SD

nSD

nPGOOD

NC

RTN

NC

UVLORTN

LM5073

1

2

3

4

5

7

6

14

13

12

11

10

8

9

LM5073

SNVS490C – MARCH 2007 – REVISED APRIL 2013

www.ti.com

Connection Diagram

14 Lead HTSSOP-EP

PIN DESCRIPTIONS

Pin Number

Name

Description

1

UVLORTN

Return for the external UVLO programming resistor divider.

2

UVLO

Line under-voltage lockout programming pin.

3

VIN

Positive supply pin for the PD interface and the DC-DC converter interface.

4

RCLASS

PD Classification programming pin.

5

FAUX

Front auxiliary power enable pin.

6

DCCL

PD interface DC current limit programming pin.

Negative supply pin for the PD interface; connected to PoE and/or front auxiliary

7

VEE

power return path.

8

NC

No internal connection.

DC-DC converter power return; connected to the drain of the internal PD interface

9

RTN

hot swap MOSFET.

10

NC

No internal connection.

PD interface power good delay and indicator. nPGOOD is low when the hot swap

11

nPGOOD

MOSFET drain to source voltage is less than 1.5V.

Open drain, active low shut down signal to the DC-DC converter. The nSD pin

12

nSD

switches to the high impedance state when nPGOOD is less than 2.5V.

Open drain, active high shut down signal to the DC-DC converter. The SD pin

13

SD

switches to the low state when nPGOOD is less than 2.5V.

14

RAUX

Rear auxiliary power enable pin, and dominant/non-dominant selection.

Exposed metal pad on the underside of the device. It is recommended to connect

EP

this pad to a PC Board plane connected to the VEE pin to improve heat dissipation.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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