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Oct10-07 RevJ

SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator

© 2007 Sipex Corporation

APPLICATIONS INFORMATION

Figure 4. Typical SP6652 circuit layout.

Bode plot) divided by the loop gain band-

width, given as 20kHz, which is used in the

following equation:

Error Amp Gain

/ (loop gain bandwidth)

= 80kHz / 20kHz

= 4

The error amp transconductance is about

Rz = 4/1mS = 4KΩ

compensation.

The zero for loop compensation is placed

at the first modulator pole of 4 kHz to pro-

vide a loop response of -20/dB/decade at

the crossover frequency. The compensa-

tion capacitor Cc can be calculated from

value:

= 10nF

From the Typical Performance Charac-

teristics load step curves, the 2.5V output

recommended.