LM4937RLSLASHNOPB datasheet(21/41 Pages) TI1

21 / 41 page

LM4937

www.ti.com

SNAS369J – OCTOBER 2006 – REVISED MAY 2013

Fs (kHz)

DAC Oversampling Ratio

Required CLock at DAC Clock Generator

Input (MHz)

22.05

125

5.5125

22.05

128

5.6448

125

128

6.144

125

128

8.192

44.1

125

11.025

44.1

128

11.2896

125

128

12.288

88.2

11.2896

12.288

176.4

22.5792

192

24.576

Methods for producing these clock frequencies are described in the PLL CONFIGURATION REGISTERS

section.

The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample

rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and

disabling the PLL. In this way we can save power and the clock jitter will be low.

R_DIV

Divide Value

DAC Clock Generator Input

Sample Rate Supported <KHz>

Frequency <MHz>

2.4

9.6

2.5

4.8

19.2

1.5

The R divider can also be used along with the P divider in order to create the clock needed to support low

sample rates.

DAC SETUP REGISTER

This register is used to configure the basic operation of the stereo DAC.

Table 20. DAC_SETUP (0Eh)

(Set = logic 1, Clear = logic 0)

Bits

Description

1:0

DAC_MODE

The DAC used in the LM4937 can operate in one of 4 oversampling modes.

The modes are described as follows:

DAC_MODE

Oversampling Rate

Typical FS

Clock Required

125

48KHz

12.000MHz (USB Mode)

128

44.1KHz

11.2896MHz

48KHz

12.288MHz

96KHz

12.288MHz

192KHz

24.576MHz

MUTE_L

Mutes the left DAC channel on the next zero crossing.

MUTE_R

Mutes the right DAC channel on the next zero crossing.

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