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SP332 датащи(PDF) 7 Page - Exar Corporation |
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SP332 датащи(HTML) 7 Page - Exar Corporation |
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7 / 11 page ![]() 7 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 50-668-707 • www.exar.com SP332_00_0260 Since both V+ and V– are separately gen- erated from V CC in a no–load condition, V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 15kHz. The external capaci- tors must be 0.1µF with a 16V breakdown rating. Phase 3 — V DD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C produces –5V in the negative terminal of C , which is applied to the negative side of capacitor C 2. Since C2 + is at +5V, the voltage potential across C 2 is l0V. Phase 4 — V DD transfer — The fourth phase of the clock connects the negative terminal of C 2 to ground and transfers the generated l0V across C 2 to C4, the VDD storage capacitor. Again, simultaneously with this, the positive side of capacitor C is switched to +5V and the negative side is connected to ground, and the cycle begins again. +10V GND GND -10V a) C2+ b) C2- Figure 7. Charge Pump Waveforms VCC = +5V –5V –5V +5V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + + + – – – – Figure 8. Charge Pump Phase 1. VCC = +5V –10V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + + + – – – – Figure 10. Charge Pump Phase 2. VCC = +5V –5V +5V –5V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + + + – – – – Figure 9. Charge Pump Phase 3. VCC = +5V +10V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + + + – – – – Figure 11. Charge Pump Phase 4. |
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