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STA310 датащи(PDF) 7 Page - STMicroelectronics

номер детали STA310
подробное описание детали  62-CH. MULTISTANDARD AUDIO DECODER
PDF  90 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STA310 датащи(HTML) 7 Page - STMicroelectronics

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STA310
• Data From a Prologic downmix (encoder)
“Lrclk” “Sclk” “PcmClk”
- S/P DIF Output
2.1.3 Control I/F
I2C slave or parallel interface:
The device configuration and the command issuing is done via this interface. To facilitate the contact with the
MCU, 2 interrupt lines (IRQB and INTLINE) are available.
3
ARCHITECTURE OVERVIEW
3.1 Data flow
The STA310 is based on a programmable MMDSP+ core optimized for audio decoding algorithms.
Dedicated hardware has been added to perform specific operations such as bitstream depacking or IEC data
formatting.
The arrows in Figure 3 indicate the data flow within the chip.
The compressed bitstream is input via the data input interface.
Data are transferred on a byte basis to the FIFO. This FIFO allows burst input data at up to 33Mbit/s.
The input processor, which is composed of a packet parser and an audio parser, unpacks the bitstream (Packet
parser) and verifies the syntax of the incoming stream (audio parser).
The compressed audio frames with their associated information (PTS) are stored into the circular frame buffer.
While a second frame is stored in the circular frame buffer, the first frame is extracted by the audio core decoder
which decodes it to produce audio samples.
The PCM unit converts the samples to the PCM format. The PCM unit controls also the channel delay buffer in
order to delay each channel independently.
In parallel, the IEC unit transmits non compressed data or compressed data according to the selected mode. In
the compressed mode, the data are extracted directly from the circular buffer and formatted according to the
IEC-61937 standard. In non compressed mode, the left and right PCM channels formatted by the PCM unit are
output by the IEC unit, according to the SPDIF standard
Figure 1. Architecture and data flows
1
DATAIN
INPUT DATA
INTERFACE
HOST
INTERFACE
CONTROL,
STATUS
CLOCKS
2
FIFO
256 x 8
INPUT
PROCESSOR
CIRCULAR FRAME BUFFER
3
4
CORE AUDIO
IEC958
FORMATER
PCM UNIT
CHANNEL DELAY
BUFFER (35ms)
DECODER
6
7
8
IEC958
(1937)
OUT
PCMOUT
5



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