TABLE IV Encoding State Table

NRZIO

CODEOUT

CURRENT

STATE

ML

17 OUT

STATE

NEXT

SS

BB

00

0

0

1

0

0

00

1

0

1

0

2

01

0

0

1

0

4

01

1

0

1

0

3

10

0

0

0

0

0

10

1

0

0

0

2

11

0

0

0

0

4

11

1

0

0

0

3

20

0

1

0

0

0

20

1

1

0

0

2

21

0

1

0

0

4

21

1

1

0

0

3

30

0

1

0

1

0

30

1

1

0

1

1

31

0

1

0

1

4

31

1

1

0

0

1

40

0

0

0

1

0

40

1

0

0

1

1

41

0

0

0

1

4

41

1

0

1

0

1

Precompensation Outputs

The precompensation circuit in this ENDEC generates out-

put data to be used externally to provide write precompen-

sation The precompensation truth table (Table V) demon-

strates what outputs are expected per data sequence (bit

stream) In the table the bit which is being considered for

precompensation is the target bit T This target bit is a logi-

cal high level The location of data bits on either side of the

target bit indicates the logic states of the precompensation

outputs No shift indicates that all the precompensation out-

puts are at a logical low level The mention of a precompen-

sation output in the ‘‘FUNCTION’’ column indicates that it is

at a logical high while those not mentioned are at a logical

low level

TABLE V Precompensation Truth Table

BIT STREAM

FUNCTION

MSB

LSB

0

0

T

0

0

NO SHIFT

1

0

T

0

1

NO SHIFT

1

0

T

0

0

EARLY

0

0

T

0

1

LATE

The EARLY and LATE outputs need to be connected to

inputs of a precompensation circuit to achieve write pre-

compensation Using the NSC DP8492 device as an exam-

ple the EARLY and LATE outputs of the ENDEC will be

connected to the EARLY and LATE inputs to the DP8492

respectively

Address Mark Mode

Hard Sectored Read Mode

(Figure 13)

This ENDEC supports only a 3T preamble pattern At the

assertion of READ GATE the decoder searches for 16 un-

interrupted code pulses of (3T) preamble Once the pream-

ble counter has filled to a count of 16 an internal preamble

detected signal is issued It resets an internal state machine

and initiates the phase synchronization process Decoding

of 17 data will begin after phase synchronization

Hard Sectored Write Mode

(Figure 12)

At the assertion of WRITE GATE with NRZIO inputs held

low the encoder issues (3T) preamble at the CODEOUT

pin Preamble will continue until the first non-zero NRZ input

bit appears

TLF11963 – 9

FIGURE 12 Hard Sectored Write Mode Waveforms

TLF11963 – 10

FIGURE 13 Hard Sectored Read Mode Waveforms

14