LM3560 datasheet(41/48 Pages) TI1

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1.1

1.2

1.3

1.4

1.5

100 105 110

TEMPERATURE (°C)

VBIAS = 2.5V,

@ +25°C, B = 4500,

R3 = 9 k:

RTHERMISTOR = 100 k:

( )

(

)

93 273

298

R T

100 k

6.047 k

2.5 V

R3 is then :

9.071k

W ´

LM3560

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SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013

(6)

Figure 46 shows the linearity of the thermistor resistive divider of the previous example.

Figure 46. Thermistor Resistive Divider Response vs Temperature

Layout Recommendations

The high switching frequency and large switching currents of the LM3560 make the choice of layout important.

The following steps should be used as a reference to ensure the device is stable and maintains proper LED

current regulation across its intended operating voltage and current range.

1. Place CIN on the top layer (same layer as the LM3560) and as close to the device as possible. The input

capacitor conducts the driver currents during the low side MOSFET turn-on and turn-off and can see current

spikes over 1A in amplitude. Connecting the input capacitor through short wide traces to both the IN and

GND terminals will reduce the inductive voltage spikes that occur during switching and which can corrupt the

VIN line.

2. Place COUT on the top layer (same layer as the LM3560) and as close as possible to the OUT and GND

terminal. The returns for both CIN and COUT should come together at one point, and as close to the GND pin

as possible. Connecting COUT through short wide traces will reduce the series inductance on the OUT and

GND terminals that can corrupt the VOUT and GND line and cause excessive noise in the device and

surrounding circuitry.

3. Connect the inductor on the top layer close to the SW pin. There should be a low-impedance connection

from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the

SW node should be small so as to reduce the capacitive coupling of the high dV/dt present at SW that can

couple into nearby traces.

4. Avoid routing logic traces near the SW node so as to avoid any capacitively coupled voltages from SW onto

any high-impedance logic lines such as TX1/TORCH/GPIO1, TX2/INT/GPIO2, HWEN, LEDI/NTC (NTC

mode), SDA, and SCL. A good approach is to insert an inner layer GND plane underneath the SW node and

between any nearby routed traces. This creates a shield from the electric field generated at SW.

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