1

bit6

F2

bit5

1

bit7

F1

bit4

F0

bit3

T2

bit2

T1

bit1

T0

bit0

MSB

LSB

Current Control Register

Register Address: 0xA0

IND EN

bit7

A/T EN

bit6

FGATE

bit5

CM1

bit4

CM0

bit3

FLASH

bit2

CHARGE

bit1

TORCH

bit0

MSB

LSB

General Purpose Register

Register Address: 0x10

LM3550

www.ti.com

SNVS569B – MAY 2009 – REVISED MAY 2013

General Purpose Register Description

FLASH, CHARGE, and TORCH: Mode Bits (see Table 1 below).

CM0–CM1: Capacitor Charge Mode (see Table 2 below).

FGATE: Flash Gate Bit. If FGATE is a ‘0’, then an end-of-charge condition must occur before a flash can take

place. If FGATE is a ‘1’, then an end-of-charge condition does not have to occur before a flash can take place.

A/T EN: ALD/TEMP Enable Bit

IND EN: Enable Indicator Current Source ('0' = Indicator Off, '1' = Indicator On)

Table 1. Control Modes

Flash

Charge

Torch

Mode

0

0

0

Disabled

0

0

1

Torch

0

1

0

Charge

0

1

1

Charge and Torch

1

x

x

Flash

Table 2. Capacitor Charge Level

CM1

CM0

Level

0

0

Optimal Charge Mode

0

1

4.5

1

0

5.0V

1

1

5.3V

Table 3. Gated Flash Control

FGATE Bit

Result

0

Flash only allowed after EOC reached

1

Flash allowed without EOC reached

Table 4. ALD/TEMP Control

A/T EN Bit

Result

0

ALD MODE DISABLED

1

ALD MODE ENABLED

Current Control Register Description

Table 5. Torch Level Table

T2

T1

T0

Level

0

0

0

60 mA

0

0

1

80 mA

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