tantalum capacitor is recommended. The input supply

should be further bypassed with a 0.01 µF - 0.1 µF ceramic

capacitor, placed close to the device. The ceramic capacitor

reduces ringing on the supply that can occur when a short is

present at the output of a port.

EXTENDING THE FAULT FLAG DELAY

While the 7 ms (typical) internal delay in reporting flag con-

ditions is adequate for most applications, the delay can be

extended by connecting external RC filters to the FLAG pins,

as shown in Figure 5.

POWER DISSIPATION AND JUNCTION TEMPERATURE

A few simple calculations will allow a designer to calculate

the approximate operating temperature of the LM3544 for a

given application. The large currents possible through the

low resistance power MOSFET combined with the high ther-

mal resistance of the SOIC package, in relation to power

packages, make this estimate an important design step.

Begin the estimate by determining R

operating temperature using the graphs in the Typical Per-

formance Characteristics section of this datasheet. Next,

calculate the power dissipation through the switch with

Equation (1).

PD=R

2

(1)

Note: Equation for power dissipation neglects portion that

comes from LM3544 quiescent current because this value

will almost always be insignificant.

Using this figure, determine the junction temperature with

Equation (2).

T

θ

(2)

Where:

θ

Temperature (˚C).

Compare the calculated temperature with the expected tem-

perature used to estimate R

match, re-estimate R

temperature and repeat the calculations. Reiterate as nec-

essary.

PCB LAYOUT CONSIDERATIONS

In order to meet the USB requirements for voltage drop,

droop and EMI, each component used in this circuit must be

evaluated for its contribution to the circuit performance.

These principles are illustrated in Figure 6. The following

PCB layout rules and guidelines are recommended

1.

Place the switch as close to the USB connector as

possible. Keep all V

use at least 50-mil, 1 ounce copper for all V

Solder plating the traces will reduce the trace resistance.

2.

Avoid vias as much as possible. If vias are used, use

multiple vias in parallel and/or make them as large as

possible.

3.

Place the output capacitor and ferrite beads as close to

the USB connector as possible.

4.

If ferrite beads are used, use wires with minimum resis-

tance and large solder pads to minimize connection

resistance.

10120828

FIGURE 5. Typical Circuit for Lengthening the Internal

Flag Delay

10120827

FIGURE 6. Self-Powered Hub Connections and Per-Port Voltage Drop

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