VT8501 datasheet(7/17 Pages) ETC

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VT8501 Apollo MVP4

Revision 1.3 February 1, 2000

-1-

Features

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VIA VT8501

APOLLO MVP4

66 / 100 MHz

Single-Chip Socket-7 / Super-7 North Bridge

with PCI System Bus,

Integrated AGP 2D / 3D Graphics Accelerator

and Advanced ECC Memory Controller

supporting PC100 SDRAM,

Virtual Channel SDRAM, EDO, and FPG DRAM

• General

− 492 BGA Package (35mm x 35mm )

− 2.5 Volt +/- 0.2V Core

− Supports separately powered 3.3V tolerant interface to CPU and Memory

− Supports separately powered 5.0V tolerant interface to PCI bus and Video interface

− 2.5V, 0.25um, high speed / low power CMOS process

− PC-98/99 compatible using VIA VT82C686A (352-pin BGA) south bridge chip

− 66 / 100 MHz Operation

CPU

Internal

AGP

DRAM

/ VGC

PCI

Comments

100 MHz

66 MHz

100 MHz

33 MHz

synchronous (DRAM uses CPU clock)

66 MHz

33 MHz

synchronous (DRAM uses CPU clock)

66 MHz

100 MHz

33 MHz

Up pseudo-synchronous (DRAM uses MEM clock)

• Socket 7 Host Interface

− Supports all Socket-7 / Super-7 processors including 64-bit Intel Pentium™ / Pentium™ with MMX™ , AMD

6K86™ (K6™ and K6-2™), Cyrix/IBM 6x86™ / 6x86MX™ , IDT/Centaur C6, and Rise MP6 CPUs

− 66 / 100 MHz CPU “Front Side Bus”

− Supports 3.3V and sub-3.3V interface to CPU

− Built-in de-skew PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions

− Cyrix/IBM 6x86™ linear burst support

− AMD K6™ and K6-2™ write allocation support

− Supports CPU-to-DRAM write combining

− System management interrupt, memory remap and stop clock mechanisms

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