LM3203TLXSLASHNOPB datasheet(4/22 Pages) TI1

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LM3203

SNVS355D – MAY 2005 – REVISED APRIL 2013

www.ti.com

ELECTRICAL CHARACTERISTICS

(1) (2)

Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature

range (

−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, specifications apply to the LM3203 with: PVIN = VDD = EN = 3.6V,

BYP = 0V, VCON = 0.267V.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

VIN

Input Voltage Range(3)

PVIN = VDD = VIN

2.7

5.5

VFB, MIN

Feedback Voltage at

VCON = 0.267V, VIN = 3.6V

0.250

0.267

0.284

Minimum Setting

VFB, MAX

Feedback Voltage at

VCON = 1.20V, VIN = 4.2V

1.176

1.200

1.224

Maximum Setting

OVP

Over-Voltage Protection

See(4)

100

150

Threshold

ISHDN

Shutdown Supply

EN = SW = BYPOUT = VCON = FB = 0V

0.1

µA

Current(5)

IQ_PWM

DC Bias Current into

VCON = 0.267V, FB = 2V, BYPOUT = 0V, No

675

780

µA

VDD

Switching

IQ_BYP

BYP = 3.6V, VCON = 0.5V, No Load

680

780

µA

RDSON (P)

Pin-Pin Resistance for

ISW = 500mA

320

450

Ω

P-FET

RDSON (N)

Pin-Pin Resistance for

ISW = − 200mA

310

450

Ω

N-FET

RDSON

Pin-Pin Resistance for

IBYPOUT = 500mA

120

Ω

(BYP)

Bypass FET

ILIM-PFET

Switch Current Limit

See(6)

700

820

940

ILIM-BYP

Bypass FET Current

See(7)

800

1000

1200

Limit

FOSC

Internal Oscillator

1.7

2.2

MHz

Frequency

VIH

Logic High Input

1.20

Threshold for EN, BYP

VIL

Logic Low Input

0.4

Threshold for EN, BYP

IPIN

Pin Pull Down Current

EN, BYP = 3.6V

µA

for EN, BYP

Gain

VCON to VOUT Gain

V/V

ZCON

VCON Input Resistance

VCON = 1.2V

Ω

(1)

All voltages are with respect to the potential at the GND pins.

(2)

Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most

likely norm.

(3)

The LM3203 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where

requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should

be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V.

(4)

Over-Voltage protection (OVP) threshold is the voltage above the nominal VOUT where the OVP comparator turns off the PFET switch

while in PWM mode. The OVP threshold will be the value of the threshold at the FB voltage times the resistor divider ratio. In the

Figure 31, 100mV (typ.) × ((267K + 133K) ÷ 133K).

(5)

Shutdown current includes leakage current of PFET and Bypass FET.

(6)

Electrical Characteristics table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current

limit is activated). Refer to Typical Performance Characteristics (Open/Closed Loop Current Limit vs Temperature (PWM Mode) curve)

for closed loop data and its variation with regards to supply voltage and temperature. Closed loop current limit is the peak inductor

current measured in the application circuit by increasing output current until output voltage drops by 10%.

(7)

Bypass FET current limit is defined as the load current at which the FB voltage is 1V lower than VIN.

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