PC87391 datasheet(63/148 Pages) NSC

номер детали	PC87391

подробное описание детали	100-Pin LPC SuperI/O Devices for Portable Applications

PDF	148 Pages

Scroll/Zoom	100%

производитель	NSC [National Semiconductor (TI)]

домашняя страница	http://www.national.com

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63 / 148 page

2.0 Device Architecture and Configuration (Continued)

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Usage Hints: To operate GMP enhanced features, make sure to locate its base address within the LPC Wide Generic ad-

dress range.

When bit 3 of the GMP configuration register is set to 0 (default), the GMP operates in Legacy mode. In this mode, only the

Game Port Legacy Status (GMPLST) register of the GMP is accessible, and is mapped to the base address of the GMP.

For example, if GMP configuration bit 3 is set to 0 and the base address is programmed to 203h, the GMPLST register is

mapped to address 203h, and is the only user-accessible GMP register.

The GMP is also forced to operate in Legacy mode if the programmed base address is not 16-byte aligned; i.e. bits 3-0 of

the base address are not all 0’s.

When bit 3 of the GMP register is set to 1 and the programmed GMP base address is 16-byte aligned; i.e., bits 3-0 of the

base address are all 0’s, the GMP can be operated in Enhanced mode. In this condtion, all the registers listed in the GMP

chapter are accessible.

PC87391 датащи(PDF) 63 Page - National Semiconductor (TI)