DP83950B datasheet(23/80 Pages) NSC

23 / 80 page

50 Functional Description

The IEEE repeater specification details a number of func-

tions a repeater system must perform These requirements

allied with a need for the implementation to be multiport

strongly favors the choice of a modular design style In such

a design functionality is split between those tasks common

to all data channels and those exclusive to each individual

channel The RIC follows this approach certain functional

blocks are replicated for each network attachment (also

known as a repeater port) and others are shared The fol-

lowing section briefly describes the functional blocks in the

RIC

51 OVERVIEW OF RIC FUNCTIONS

Segment Specific Block Network Port

As shown in the Block Diagram the segment specific blocks

consist of

1 One or more physical layer interfaces

2 A logic block required for performing repeater operations

upon that particular segment This is known as the ‘‘port’’

logic since it is the access ‘‘port’’ the segment has to the

rest of the network

This function is repeated 13 times in the RIC (one for each

port) and is shown on the right side of the Block Diagram

Figure 51

The physical layer interfaces provided depends upon the

port under examination Port 1 has an AUI compliant inter-

face for use with AUI compatible transceiver boxes and ca-

ble Ports 2 to 13 may be configured for use with one of two

interfaces twisted pair or an external transceiver The for-

mer utilizes the RIC’s on-chip 10BASE-T transceivers the

latter allows connection to external transceivers When us-

ing the external transceiver mode the interface is AUI com-

patible Although AUI compatible transceivers are support-

ed the interface is not designed for use with an interface

cable thus the transceivers are necessarily internal to the

repeater equipment

Inside the port logic there are 3 distinct functions

1 The port state machine ‘‘PSM’’ is required to perform

data and collision repetition as described by the repeater

specification for example it determines whether this port

should be receiving from or transmitting to its network

segment

2 The port partition logic implements the segment partition-

ing algorithm This algorithm is defined by the IEEE speci-

fication and is used to protect the network from malfunc-

tioning segements

3 The port status register reflects the current status of the

port It may be accessed by a system processor to obtain

this status or to perform certain port configuration opera-

tions such as port disable

Shared Functional Blocks

Repeater Core Logic

The shared functional blocks consist of the Repeater Main

State Machine (MSM) and Timers a 32 bit Elasticity Buffer

PLL Decoder

and Receive and Transmit Multiplexors

These blocks perform the majority of the operations needed

to fulfill the requirements of the IEEE repeater specification

When a packet is received by a port it is sent via the Re-

ceive Multiplexor to the PLL Decoder Notification of the

data and collision status is sent to the main state machine

via the receive multiplexor and collision activity status sig-

nals This enables the main state machine to determine the

source of the data to be repeated and the type of data to be

transmitted The transmit data may be either the received

packet’s data field or a preamblejam pattern consisting of

a 1010

bit pattern

Associated with the main state machine are a series of tim-

ers These ensure various IEEE specification times (referred

to as the TW1 to TW6 times) are fulfilled

A repeater unit is required to meet the same signal jitter

performance as any receiving node attached to a network

segment Consequently a phase locked loop Manchester

decoder is required so that the packet may be decoded and

the jitter accumulated over the receiving segment recov-

ered The decode logic outputs data in NRZ format with an

associated clock and enable In this form the packet is in a

convenient format for transfer to other devices such as net-

work controllers and other RICs via the Inter-RIC bus (de-

scribed later) The data may then be re-encoded into Man-

chester data and transmitted

Reception and transmission via physical layer transceiver

units causes a loss of bits in the preamble field of a data

packet The repeater specification requires this loss to be

compensated for To accomplish this an elasticity buffer is

employed to temporarily store bits in the data field of the

packet

The sequence of operation is as follows

Soon after the network segment receiving the data packet

has been identified the RIC begins to transmit the packet

preamble pattern (1010

) onto the other network seg-

ments While the preamble is being transmitted the Elastici-

ty Buffer monitors the decoded received clock and data sig-

nals (this is done via the Inter-RIC bus as described later)

When the start of frame delimiter ‘‘SFD’’ is detected the

received data stream is written into the elasticity buffer Re-

moval of data from the buffer for retransmission is not al-

lowed until a valid length preamble pattern has been trans-

mitted

Inter-RIC Bus Interface

Using the RIC in a repeater system allows the design to be

constructed with many more network attachments than can

be supported by a single chip The split of functions already

described allows data packets and collision status to be

transferred between multiple RICs and at the same time the

multiple RICs still behave as a single logical repeater Since

all RICs in a repeater system are identical and capable of

performing any of the repetition operations the failure of

one RIC will not cause the failure of the entire system This

is an important issue in large multiport repeaters

RICs communicate via a specialized interface known as the

Inter-RIC bus This allows the data packet to be transferred

from the receiving RIC to the other RICs in the system

These RICs then transmit the data stream to their seg-

ments Just as important as data transfer is the notification

of collisions occurring across the network The Inter-RIC

bus has a set of status lines capable of conveying collision

information between RICs to ensure their main state ma-

chines operate in the appropriate manner

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