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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83936AVF датащи(PDF) 66 Page - National Semiconductor (TI) |
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DP83936AVF датащи(HTML) 66 Page - National Semiconductor (TI) |
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66 / 104 page  70 Bus Interface (Continued) 7355 Memory Cycle for BMODE e 0 Asynchronous Mode On the rising edge of T1 the SONIC-T asserts ADS and ECS to indicate that the memory cycle is starting The ad- dress (A31 – A1) bus status (S2 – S0) and the direction strobe (MWR) are driven and do not change for the remain- der of the memory cycle On the falling edge of T1 the SONIC-T deasserts ECS ADS is deasserted on the rising edge of T2 In Asynchronous mode RDYi is asynchronously sampled on the falling edge of both T1 and T2 RDYi does not need to be synchronized to the bus clock because the chip al- ways resolves these signals to either a high or low state Meeting the setup time for RDYi guarantees that the SONIC-T will terminate the memory cycle 15 bus clocks after RDYi was sampled T2 states will be repeated until RDYi is sampled properly in a low state (see note below) During read cycles ( Figures 7-14 and 7-15 ) data (D31 – D0) is latched at the falling edge of T2 and DS is asserted at the rising edge of T1 For write cycles ( Figures 7-16 and 7-17 ) data is driven on the falling edge of T1 If there are wait states inserted DS is asserted on the rising edge of the first T2 (wait) DS is not asserted for zero wait state write cycles The SONIC-T terminates the memory cycle by deasserting DS at the falling edge of T2 Note If the setup time for RDYi is met during T1 the full asynchronous bus cycle will take only 2 bus clocks This may be an unwanted situation If so RDYi should be deasserted during T1 TLF12597 – 41 FIGURE 7-14 Memory Read BMODE e 0 Asynchronous (1 Wait-State) TLF12597 – 42 FIGURE 7-15 Memory Read BMODE e 0 Asynchronous (2 Wait-State) http www nationalcom 66 |
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