WM8994 datasheet(49/359 Pages) WOLFSON

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Production Data

WM8994

PD, April 2012, Rev 4.4

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

IN2LN_TO_IN2L

IN2L PGA Inverting Input Select

0 = Not connected

1 = Connected to IN2LN

IN1LP_TO_IN1L

IN1L PGA Non-Inverting Input Select

0 = Connected to VMID

1 = Connected to IN1LP

Note that VMID_BUF_ENA must be

set when using IN1L connected to

VMID.

IN1LN_TO_IN1L

IN1L PGA Inverting Input Select

0 = Not connected

1 = Connected to IN1LN

IN2RP_TO_IN2R

IN2R PGA Non-Inverting Input Select

0 = Connected to VMID

1 = Connected to IN2RP

Note that VMID_BUF_ENA must be

set when using IN2R connected to

VMID.

IN2RN_TO_IN2R

IN2R PGA Inverting Input Select

0 = Not connected

1 = Connected to IN2RN

IN1RP_TO_IN1R

IN1R PGA Non-Inverting Input Select

0 = Connected to VMID

1 = Connected to IN1RP

Note that VMID_BUF_ENA must be

set when using IN1R connected to

VMID.

IN1RN_TO_IN1R

IN1R PGA Inverting Input Select

0 = Not connected

1 = Connected to IN1RN

Table 3 Input PGA Configuration

INPUT PGA VOLUME CONTROL

Each of the four Input PGAs has an independently controlled gain range of -16.5dB to +30dB in 1.5dB

steps. The gains on the inverting and non-inverting inputs to the PGAs are always equal. Each Input

PGA can be independently muted using the PGA mute bits as described in Table 4, with maximum

mute attenuation achieved by simultaneously disconnecting the corresponding inputs described in

Table 3.

Note that, under default conditions (following power-up or software reset), the PGA mute register bits

are set to ‘1’, but the mute functions will only become effective after the respective bit has been

toggled to ‘0’ and then back to ‘1’. The Input PGAs will be un-muted (Mute disabled) after power-up or

software reset, regardless of the readback value of the respective PGA mute bits.

To prevent "zipper noise", a zero-cross function is provided on the input PGAs. When this feature is

enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long

period without zero-crossings, a timeout function is provided. When the zero-cross function is

enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The

timeout clock is enabled using TOCLK_ENA, the timeout period is set by TOCLK_DIV. See “Clocking

and Sample Rates” for more information on these fields.

The IN1_VU and IN2_VU bits control the loading of the input PGA volume data. When IN1_VU and

IN2_VU are set to 0, the PGA volume data will be loaded into the respective control register, but will

not actually change the gain setting. The IN1L and IN1R volume settings are both updated when a 1

is written to IN1_VU; the IN2L and IN2R volume settings are both updated when a 1 is written to

IN2_VU. This makes it possible to update the gain of the left and right signal paths simultaneously.

The Input PGA Volume Control register fields are described in Table 4 and Table 5.

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