60 Pin Descriptions

28-Pin PLCC

16-Pin DIP

Name

IO

Description

21

O

Collision Output

Balanced differential line driver outputs from the collision detect

circuitry The 10 MHz signal from the internal oscillator is transferred to these

32

outputs in the event of collision excessive transmission (jabber) or during CD

Heartbeat condition These outputs are open emitters pulldown resistors to VEE

are required When operating into a 78X transmission line these resistors should

be 500X In Cheapernet applications where the 78X drop cable is not used

higher resistor values (up to 15k) may be used to save power

43

O

Receive Output

Balanced differential line driver outputs from the Receiver These

outputs also require 500X pulldown resistors

12

6

13

7

I

Transmit Input

Balanced differential line receiver inputs to the Transmitter The

common mode voltage for these inputs is determined internally and must not be

14

8

externally established Signals meeting Transmitter squelch requirements are

waveshaped and output at TXO

15

9

HBE

I

Heartbeat Enable

This input enables CD Heartbeat when grounded disables it

when connected to VEE

18

11

I

External Resistor

A fixed 1k 1% resistor connected between these pins

establishes internal operating currents

19

12

26

14

RXI

I

Receive Input

Connects directly to the coaxial cable Signals meeting Receiver

squelch requirements are equalized for inter-symbol distortion amplified and

28

15

TXO

O

Transmit Output

Connects either directly (Cheapernet) or via an isolation diode

(Ethernet) to the coaxial cable

1

16

CDS

I

Collision Detect Sense

Ground sense connection for the collision detect circuit

This pin should be connected separately to the shield to avoid ground drops from

altering the receive mode collision threshold

16 17

10

GND

Positive Supply Pin

A 01 mF ceramic decoupling capacitor must be connected

across GND and VEE as close to the device as possible

5–11

4

VEE

Negative Supply Pins

In order to make full use of the 35W power dissipation

capability of this package these pins should be connected to a large metal frame

20–25

5

area on the PC board Doing this will reduce the operating die temperature of the

13

device thereby increasing the long term reliability

61 PC BOARD LAYOUT

The DP8392C package is uniquely designed to ensure that

the device meets the 1 million hour Mean Time Between

Failure (MTBF) requirement of the IEEE 8023 standard In

order to fully utilize this heat dissipation design the three

should be included in the printed circuit board layout

There are two basic considerations in designing a PCB for

the DP8392C and C-1 CTI The first is ensuring that the

layout does not degrade the electrical characteristics of the

DP8392 and enables the end product to meet the IEEE

8023 specifications The second consideration is meeting

the thermal requirements to the DP8392

Since the DP8392 is highly integrated the layout is actually

quite simple and there are just a few guidelines

1 Ensure that the parasitic capacitance added to the RXI

and TXO pins is minimized To do this keep these signal

traces short and remove any power planes under these

signals and under any components that connect to these

signals

Figure 6 shows the component placement for the

DIP package The PLCC component placement would be

similar as shown in

Figure 7

2 The power supply layout to the CTI should be relatively

clean Usually the CTI’s power is supplied directly by a

DC-DC converter The power should be routed either

through separate isolated planes or via thick PCB traces

For the second consideration the packaged DP8392 must

have a thermal resistance of 40 C–45 CW to meet the full

0 C–70 C temperature range The CTI dissipates more

power when transmitting than while it is idle In order to do

this the thermal resistance of the device must be 40 C–

45 CW To meet this requirement during transmission it is

recommended that a small printed circuit board plane be

The size of the trace plane depends on the package used

and the duty cycle of transmissions For the DIP package

the plane should be connected to pins 4 – 5 13 and the size

should be approximately 02 square inches for applications

This would be typical of adapter or motherboard applica-

tions In applications where the transmitter duty cycle may

be large (repeaters and external transceivers) the total area

Figure 6 illustrates a recom-

mended component side layout for these planes

5