ADUC702 datasheet(21/80 Pages) AD

21 / 80 page

Preliminary Technical Data

ADuC702x Series

Rev. PrB | Page 21 of 80

MEMORY ORGANISATION

The part incorporates two separate blocks of memory, 8kByte of

SRAM and 64kByte of On-Chip Flash/EE memory. 62kByte of

On-Chip Flash/EE memory are available to the user, and the

remaining 2kBytes are reserved for the factory configured boot

page. These two blocks are mapped as shown in

Figure 4

Note that by default, after a reset, the Flash/EE memory is

mirrored at address 0x00000000. It is possible to remap the

SRAM at address 0x00000000 by clearing bit 0 of the REMAP

MMR. This remap function is described in more details in the

Flash/EE memory chapter.

Re-mappable Memory Space

(Flash/EE or SRAM)

Reserved

00080000h

Flash/EE

Reserved

00011FFFh

00010000h

SRAM

FFFF0000h

FFFFFFFFh

MMRs

0000FFFFh

00000000h

0008FFFFh

Figure 4: Physical memory map

Memory Access

The ARM7 core sees memory as a linear array of 232 byte

location where the different blocks of memory are mapped as

outlined in

Figure 4

The ADuC702x memory organisation is configured in little

endian format: the least significant byte is located in the lowest

byte address and the most significant byte in the highest byte

address.

Figure 5: little endian format

Flash/EE Memory

The total 64kBytes of Flash/EE are organised as 32k X 16 bits.

31k X 16 bits are user space and 1k X 16 bits is reserved for the

on chip kernel. The page size of this Flash/EE memory is

512Bytes.

62kBytes of Flash/EE are available to the user as code and non-

volatile data memory. There is no distinction between data and

program as ARM code shares the same space. The real width of

the Flash/EE memory is 16 bits, which means that in ARM

mode (32-bit instruction), two accesses to the Flash/EE are

necessary

for

each

instruction

fetch.

therefore

recommended to use Thumb mode when executing from

Flash/EE memory for optimum access speed. The maximum

access speed for the Flash/EE memory is 45MHz in Thumb

mode and 22.5MHz in full ARM mode. More details on

Flash/EE access time are outlined later in ‘Execution from

SRAM and Flash/EE’ section of this datasheet.

SRAM

8kBytes of SRAM are available to the user, organized as 2k X 32

bits, i.e. 2kWords. ARM code can run directly from SRAM at

45MHz , given that the SRAM array is configured as a 32-bit

wide memory array. More details on SRAM access time are

outlined later in ‘Execution from SRAM and Flash/EE’ section

of this datasheet.

Memory Mapped Registers

The Memory Mapped Register (MMR) space is mapped into

the upper 2 pages of the memory array and accessed by indirect

addressing through the ARM7 banked registers.

The MMR space provides an interface between the CPU and all

on-chip peripherals. All registers except the core registers

reside in the MMR area. All shaded locations shown in Figure 6

are unoccupied or reserved locations and should not be

accessed by user software. Table 6 shows a full MMR memory

map.

32 bits

Byte0

Byte1

Byte2

Byte3

0x00000000h

0x00000004h

bit0

bit31

0xFFFFFFFFh

ADUC702 датащи(PDF) 21 Page - Analog Devices

ADUC702 датащи(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL