The circuit is shown in

Figure 2 (Additional output drive may

be necessary if the oscillator must also drive other compo-

nents) When using a clock oscillator it is still recommended

that the designer connect the oscillator output to the X1 pin

and tie the X2 pin to ground

33 MANCHESTER ENCODER AND

DIFFERENTIAL DRIVER

The encoder begins operation when the Transmit Enable

input (TXE) goes high and converts clock and NRZ data to

Manchester data for the transceiver For the duration of

TXE remaining high the Transmitted Data (TXD) is encoded

rising edge of Transmit Clock (TXC) Transmission ends

when TXE goes low The last transition is always positive it

occurs at the center of the bit cell if the last bit is a one or at

the end of the bit cell if the last bit is a zero

The differential transmit pair from the secondary of the iso-

lation transformer drives up to 50 meters of twisted pair AUI

cable These outputs are source followers which require two

270X pull-down resistors to ground

The DP83910A allows both half-step and full-step to be

compatible with Ethernet I and IEEE 8023 With the SEL pin

provides zero differential voltage to operate with transform-

er coupled loads

TLF9365 – 16

FIGURE 2 DP83910A Connection for Oscillator Module

34 MANCHESTER DECODER

The decoder consists of a differential receiver and a PLL to

separate Manchester encoded data stream into clock sig-

nals and NRZ data The differential input must be externally

terminated with two 39X resistors connected in series if the

standard 78X transceiver drop cable is used in Thin-Ether-

net applications these resistors are optional To prevent

noise from falsely triggering the decoder a squelch circuit at

Once the input exceeds the squelch requirements Carrier

Sense (CRS) is asserted Receive data (RXD) and receive

clock (RXC) become valid typically within 6 bit times The

DP83910A may tolerate bit jitter up to 18 ns in the received

data

The decoder detects the end of a frame when no more

midbit transitions are detected Within one and a half bit

times after the last bit carrier sense is de-asserted Receive

clock stays active for five more bit times after CRS goes low

to guarantee the receive timings of the DP8390 NIC

35 COLLISION TRANSLATOR

When the Ethernet transceiver (DP8392 CTI) detects a colli-

sion it generates a 10 MHz signal to the differential collision

tected active the DP83910A translates the 10 MHz signal

to an active high level for the controller The controller uses

this signal to back off its current transmission and resched-

ule another one

The collision differential inputs are terminated the same way

as the differential receive inputs The squelch circuitry is

36 LOOPBACK FUNCTIONS

When the Loopback input (LBK) is asserted high the

DP83910A redirects its transmitted data back into its re-

ceive path This feature provides a convenient method for

testing both chip and system level integrity The transmit

driver and receive input circuitry are disabled in loopback

mode

40 Connection Diagrams

TLF9365 – 17

Top View

Order Number DP83910AV

See NS Package Number V28A

TLF9365 – 18

Top View

Order Number DP83910AN

See NS Package Number N24C

3