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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83902AVLC датащи(PDF) 56 Page - National Semiconductor (TI) |
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DP83902AVLC датащи(HTML) 56 Page - National Semiconductor (TI) |
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56 / 70 page  150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Control Bus Arbitration TLF11157 – 37 Symbol Parameter Min Max Units brqhl Bus Clock to Bus Request High for Local DMA 50 ns brqhr Bus Clock to Bus Request High for Remote DMA 45 ns brql Bus Request Low from Bus Clock 60 ns backs Acknowledge Setup to Bus Clock (Note 1) 2 ns bccte Bus Clock to Control Enable 60 ns bcctr Bus Clock to Control Release (Notes 2 3) 70 ns Note 1 BACK must be setup before T1 after BREQ is asserted Missed setup will slip the beginning of the DMA by four bus clocks The Bus Latency will influence the allowable FIFO threshold Note 2 During remote DMA transfers only a single bus transfer is performed During local DMA operations burst mode transfers are performed Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention 56 |
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