MSP50C30

MIXED-SIGNAL PROCESSOR

SPSS021 NOVEMBER 1998

5

POST OFFICE BOX 655303

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VT

Positive going threshold voltage (INIT)

VDD = 3.5 V

2

V

VT+

Positive-going threshold voltage (INIT)

VDD = 6 V

3.4

V

VT

Negative going threshold voltage (INIT)

VDD = 3.5 V

1.6

V

VT–

Negative-going threshold voltage (INIT)

VDD = 6 V

2.3

V

Vh

Hysteresis ( VT

VT ) (INIT)

VDD = 3.5 V

0.4

V

Vhys

Hysteresis (VT+ – VT– ) (INIT)

VDD = 6 V

1.1

V

IIkg

Input leakage current (except for OSC IN)

2

µA

Istandby

Standby current (INIT low, SETOFF)

10

µA

†

VDD = 3.3 V,

2.1

IDD†

Supply current

VDD = 5 V,

3.1

mA

DD

VDD = 6 V,

4.5

VDD = 3.3 V,

VOH = 2.75 V

–4

–12

VDD = 5 V,

VOH = 4.5 V

–5

–14

mA

IOH

High level output current (PA PB)

VDD = 6 V,

VOH = 5.5 V

–6

–15

IOH

High-level output current (PA, PB)

VDD = 3.3 V,

VOH = 2.2 V

–8

–20

VDD = 5 V,

VOH = 3.33 V

–14

–40

mA

VDD = 6 V,

VOH = 4 V

–20

–51

VDD = 3.3 V,

VOL = 0.5 V

5

9

VDD = 5 V,

VOL = 0.5 V

5

9

mA

IOL

Low level output current (PA PB)

VDD = 6 V,

VOL = 0.5 V

5

9

IOL

Low-level output current (PA, PB)

VDD = 3.3 V,

VOL = 1.1 V

10

19

VDD = 5 V,

VOL = 1.67 V

20

29

mA

VDD = 6 V,

VOL = 2 V

25

35

VDD = 3.3 V,

VOH = 2.75 V

–30

–50

VDD = 5 V,

VOH = 4.5 V

–35

–60

mA

IOH

High level output current (D/A)

VDD = 6 V,

VOH = 5.5 V

–40

–65

IOH

High-level output current (D/A)

VDD = 3.3 V,

VOH = 2.3 V

–50

–90

VDD = 5 V,

VOH = 4 V

–90

– 140

mA

VDD = 6 V,

VOH = 5 V

– 100

– 150

VDD = 3.3 V,

VOL = 0.5 V

50

80

VDD = 5 V,

VOL = 0.5 V

70

90

mA

IOL

Low level output current (D/A)

VDD = 6 V,

VOL = 0.5 V

80

110

IOL

Low-level output current (D/A)

VDD = 3.3 V,

VOL = 1 V

100

140

VDD = 5 V,

VOL = 1 V

140

mA

VDD = 6 V,

VOL = 1 V

150

Pullup resistance

Resistors selected by software and

connected between terminal and VDD

10

20

50

k

Ω

f

(l

)

Oscillator freq enc ‡

VDD = 5 V,

TA = 25°C,

14 89

15 36

15 86

MHz

fosc(low)

Oscillator frequency‡

Target frequency = 15.36 MHz

14.89

15.36

15.86

MHz

f

(hi h)

Oscillator freq enc ‡

VDD = 5 V,

TA = 25°C,

18 62

19 2

19 7

MHz

fosc(high)

Oscillator frequency‡

Target frequency = 19.2 MHz

18.62

19.2

19.7

MHz

† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output

and other outputs are open circuited.

‡ The frequency of the internal clock has a temperature coefficient of approximately – 0.2 % /

°C and a VDD coefficient of approximately ±1%/V.