ADF4153

Rev. A | Page 2 of 24

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Pin Function Descriptions...................... 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

RF Input Stage............................................................................. 10

RF INT Divider........................................................................... 10

INT, FRAC, MOD, and R Relationship.................................... 10

RF R COUNTER ........................................................................ 10

Phase Frequency Detector (PFD) and Charge Pump............ 11

MUXOUT and LOCK Detect................................................... 11

Input Shift Registers ................................................................... 11

Program Modes .......................................................................... 11

N Divider Register, R0 ............................................................... 17

R Divider Register, R1................................................................ 17

Control Register, R2 ................................................................... 17

Noise and Spur Register, R3 ...................................................... 18

Reserved Bits............................................................................... 18

RF Synthesizer: A Worked Example ........................................ 18

Modulus....................................................................................... 19

Reference Doubler and Reference Divider ............................. 19

12-Bit Programmable Modulus................................................ 19

Spurious Optimization and Fastlock ....................................... 19

Phase Resync and Spur Consistency ....................................... 19

Spurious Signals—Predicting Where They Will Appear....... 20

Filter Design—ADIsimPLL....................................................... 20

Interfacing ................................................................................... 20

PCB Design Guidelines for Chip Scale Package .................... 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

1/04—Data Sheet Changed from a REV. 0 to a REV. A

Renumbered Figures and Tables.............................. UNIVERSAL

Changes to Specifications ............................................................... 3

Changes to Pin Function Description .......................................... 7

Changes to RF Power-Down section .......................................... 17

Changes to PCB Design Guidelines for Chip Scale

Package section .............................................................................. 21

Updated Outline Dimensions ...................................................... 22

Updated Ordering Guide.............................................................. 22

7/03—Revision 0: Initial Version