ADF4107 datasheet(3/20 Pages) AD

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ADF4107

ADF4107—SPECIFICATIONS

Table 1. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA =

TMAX to TMIN, unless otherwise noted.)

Parameter

Version1

B Chips2

(Typ)

Unit

Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN)3

1.0/7.0

GHz min/max

See Figure 18 for input circuit.

RF Input Sensitivity

–5/+5

dBm min/max

Maximum Allowable Prescaler

Output Frequency4

300

MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency

20/250

MHz min/max

For f < 20 MHz, use dc-coupled square wave (0 to VDD).

REFIN Input Sensitivity5

0.8/VDD

V p-p min/max

AC-coupled; when dc-coupled, 0 to VDD, max (CMOS

compatible).

REFIN Input Capacitance

pF max

REFIN Input Current

±100

µA max

PHASE DETECTOR

Phase Detector Frequency6

104

MHz max

CHARGE PUMP

Programmable; see Figure 25.

ICP Sink/Source

High Value

mA typ

With RSET = 5.1 kΩ

Low Value

625

µA typ

Absolute Accuracy

2.5

% typ

With RSET = 5.1 kΩ

RSET Range

3.0/11

kΩ typ

See Figure 25.

ICP Three-State Leakage

nA typ

Sink and Source Current

Matching

% typ

0.5 V ≤ VCP ≤ VP – 0.5 V

ICP vs. VCP

1.5

% typ

0.5 V ≤ VCP ≤ VP – 0.5 V

ICP vs. Temperature

% typ

VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage

1.4

V min

VIL, Input Low Voltage

0.6

V max

IINH, IINL, Input Current

±1

µA max

CIN, Input Capacitance

pF max

LOGIC OUTPUTS

VOH, Output High Voltage

1.4

V min

Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V.

VOH, Output High Voltage

VDD – 0.4

V min

CMOS output chosen.

IOH

100

µA max

VOL, Output Low Voltage

0.4

V max

IOL = 500 µA

POWER SUPPLIES

AVDD

2.7/3.3

V min/V max

DVDD

AVDD

AVDD/5.5

V min/V max

AVDD ≤ VP ≤5.5V

IDD7 (AIDD + DIDD)

mA max

15 mA typ

0.4

mA max

TA = 25°C

Power-Down Mode8 (AIDD + DIDD)

µA typ

Rev. 0 | Page 3 of 20

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