DP83905AVQB datasheet(49/80 Pages) NSC

49 / 80 page

60 Operation of ATLANTIC Controller (Continued)

Error Recovery

If the packet is rejected as shown the DMA is restored by

the ATLANTIC Controller by reprogramming the DMA

starting address pointed to by the Current Page Register

Storage Format for Received Packets

The following diagrams describe the format for how re-

ceived packets are placed into memory by the local DMA

channel These modes are selected in the Data Configura-

tion Register

AD15

AD8

AD7

AD0

Next Packet Pointer

Receive Status

Receive Byte Count 1

Receive Byte Count 0

Byte 2

Byte 1

BOS e 0 WTS e 1 in Data Configuration Register This format is used with

Series 32xxx or 808xx processors

AD15

AD8

AD7

AD0

Next Packet Pointer

Receive Status

Receive Byte Count 0

Receive Byte Count 1

Byte 1

Byte 2

BOS e 1 WTS e 1 in Data Configuration Register This format is used with

680x0 type processors (Note The Receiver Count ordering remains the

same for BOS e 0or1 )

Receive Status

Next Packet Pointer

Receive Byte Count 0

Receive Byte Count 1

Byte 0

Byte 1

BOS e 0 WTS e 0 in Data Configuration Register This

format is used with general 8-bit processors

64 PACKET TRANSMISSION

The Local DMA is also used during transmission of a pack-

et Three registers control the DMA transfer during trans-

mission a Transmit Page Start Address Register (TPSR)

and the Transmit Byte Count Registers (TBCR01) When

the ATLANTIC Controller receives a command to transmit

the packet pointed to by these registers buffer memory

data will be moved into the FIFO as required during trans-

mission The ATLANTIC Controller will generate and ap-

pend the preamble synch and CRC fields

General Transmit Packet Format

Transmit

Destination Address

6 Bytes

Byte

Source Address

6 Bytes

Count

TypeLength

2 Bytes

TBCR0 1

Data

46 Bytes

Pad (If data k 46 Bytes)

Transmit Packet Assembly

The ATLANTIC Controller requires a contiguous assem-

bled packet with the format shown The transmit byte count

includes the Destination Address Source Address Length

Field and Data It does not include preamble and CRC

When transmitting data smaller than 46 bytes the packet

must be padded to a minimum size of 64 bytes The pro-

grammer is responsible for adding and stripping pad bytes

The packets are placed in the buffer RAM by the system In

IO Mode the system programs the NIC Core’s Remote

DMA to mode the data from the data port to the RAM hand-

shaking with system transfers loading the IO data port In

Shared Memory Mode the packets are written directly to the

RAM by system using standard memory transfer instruc-

tions (MOV)

For IO mode the data transfer must be 16 bits (1 word)

when in 16-bit mode and 8 bits when the ATLANTIC Con-

troller is set in 8-bit mode The data width is selected by

setting the WTS bit in the Data Configuration Register and

setting the DWlD pin for the proper mode

In Shared Memory mode data transfer can be accomplished

by using either 8- or 16-bit data transfer instructions be-

cause this mode responds to 816-bit data signalling on the

ISA bus In this mode Shared Memory Control Register 2-bit

6 sets the bus interface data width and the NIC Core’s data

width is set by the WTS bit in the Data Configuration Regis-

ter

Transmission

Prior to transmission the TPSR (Transmit Page Start Regis-

ter) and TBCR0 TBCR1 (Transmit Byte Count Registers)

must be initialized To initiate transmission of the packet the

TXP bit in the Command Register is set The Transmit

Status Register (TSR) is cleared and the ATLANTIC Con-

troller begins to prefetch transmit data from memory (unless

the ATLANTIC Controller is currently receiving) If the inter-

frame gap has timed out the ATLANTIC Controller will be-

gin transmission

Conditions Required to Begin Transmission

In order to transmit a packet the following three conditions

must be met

1 The Interframe Gap Timer has timed out the first 64 ms

of the Interframe Gap

2 At least one byte has entered the FIFO (This indicates

that the burst transfer has been started)

3 If a collision had been detected then before transmission

the packet time must have timed out

In typical systems the ATLANTIC Controller prefetches the

first burst of bytes before the 64 ms timer expires The time

during which ATLANTIC Controller transmits preamble can

also be used to load the FIFO

Note

If carrier sense is asserted before a byte has been loaded into the

FIFO the ATLANTIC Controller will become a receiver

Collision Recovery

During transmission the Buffer Management logic monitors

the transmit circuitry to determine if a collision has occurred

If a collision is detected the Buffer Management logic will

reset the FIFO and restore the Transmit DMA pointers for

retransmission of the packet The COL bit will be set in the

TSR and the NCR (Number of Collisions Register) will be

incremented If 15 retransmissions each result in a collision

the transmission will be aborted and the ABT bit in the TSR

will be set

Note

NCR reads as zeroes if excessive collisions are encountered

DP83905AVQB датащи(PDF) 49 Page - National Semiconductor (TI)

DP83905AVQB датащи(HTML) 49 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL