AD9864 datasheet(40/44 Pages) AD

40 / 44 page

AD9864

Rev. 0 | Page 40 of 44

VCO

DOUTA

CLKOUT

FREF

CLKP

CLKN

LOP

LON

IFIN

AD9864

MASTER

IOUTC

LOOP

FILTER

IOUTC

LOP

LON

IFIN

DOUTA

CLKOUT

SYNCB

DSP

CLKP

CLKN

IOUTL

TO DSP

FROM

DSP

LOOP

FILTER

CVAR

0.1

µF

LOSC

RBIAS

COSC

TO OTHER

AD9864s

FROM

CRYSTAL

OSCILLATION

VDDC

TO OTHER

AD9864s

AD9864

SLAVE

FREF

SYNCB

Figure 72. Example of Synchronizing Multiple AD9864s

Split Path Rx Architecture

A split path Rx architecture may be attractive for those applica-

tions whose instantaneous dynamic range requirements exceed

the capability of a single AD9864 device. To cope with these

higher dynamic range requirements, two AD9864s can be oper-

ated in parallel with their respective clip points offset by a fixed

amount. Adding a fixed amount of attenuation in front of the

AD9864 and/or programming the attenuation setting of its in-

ternal VGA can adjust the input-referred clip point. To save

power and simplify hardware, the LO and CLK circuits of the

device can also be shared. Connecting the SYNCB pins of the two

devices and pulsing this line low synchronizes the two devices.

An example of this concept for possible use in a GSM base sta-

tion is shown in Figure 73. The signal chain consists of a high

linearity RF front end and IF stage followed by two AD9864s

operating in parallel. The RF front end consists of a duplexer

and preselect filter to pass the GSM RF band of interest. A high

performance LNA isolates the duplexer from the preselect filter

while providing sufficient gain to minimize system NF. An RF

mixer is used to downconvert the entire GSM band to a suitable

IF, where much of the channel selectivity is accomplished. The

170.6 MHz IF is chosen to avoid any self-induced spurs from

the AD9864. The IF stage consists of two SAW filters isolated

by a 15 dB gain stage.

The cascaded SAW filter response must provide sufficient

blocker rejection in order for the receiver to meet its sensitivity

requirements under worst-case blocker conditions. A compos-

ite response having 27 dB, 60 dB, and 100 dB rejection at

frequency offsets of ±0.8 MHz, ±1.6 MHz, and ±6.5 MHz, r

spectively, provides enough blocker suppression to ensure tha

the AD9864 with the lower clip point will not be overd

any blocker. This configuration results in the best possible re

ceiver sensitivity under all blocking conditions.

riven by

The output of the last SAW filters drives the two AD9864s via a

direct signal path and an attenuated signal path. The direct path

corresponds to the AD9864 having the lowest clip point and

provides the highest receiver sensitivity with a system noise

figure of 4.7 dB. The VGA of this device is set for maximum

attenuation, so its clip point is approximately –17 dBm. Since

conversion gain from the antenna to the AD9864 is 19 dB, the

digital output of this path will nominally be selected unless the

target signal’s power exceeds –36 dBm at the antenna. The

attenuated path corresponds to the AD9864 having the highest

input-referred clip point, and its digital output point of this

path is set to 7 dBm by inserting a 30 dB attenuator and setting

the AD9864’s VGA to the middle of its 12 dB range. This

setting results in a ±6 dB adjustment of the clip point, allowing

the clip point difference to be calibrated to exactly 24 dB, so

that a simple 5-bit shift would make up the gain difference. The

attenuated path can handle signal levels up to –12 dB at the

antenna before being overdriven. Since the SAW filters provide

sufficient blocker suppression, the digital data from this path

need only be selected when the target signal exceeds –36 dBm.

Although the sensitivity of the receiver with the attenuated path

is 20 dB lower than the direct path, the strong target signal

ensures a sufficiently high carrier-to-noise ratio.

Since GSM is based on a TDMA scheme, digital data (or path)

selection can occur on a slot-by-slot basis. The AD9864 would

be configured to provide Serial I and Q data at a frame rate of

541.67 kSPS, as well as additional information including a 2-bit

reset field and a 6-bit RSSI field. These two fields contain the

information needed to decide whether the direct or attenuated

path should be used for the current time slot.

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