AD9786BSV datasheet(27/60 Pages) AD

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AD9786

Rev. 0 | Page 27 of 60

With the interpolation set to 2×, the DACCLK input runs at

twice the speed of the DATACLK. Data is latched into the

digital inputs of the AD9786 on every other rising edge of

DACCLK, as shown in Figure 47 and Figure 48. With

DCLKPOL = 0, as shown in Figure 47, the latching edge of

DACCLK is the rising edge that occurs just before the falling

edge of DATACLK. With DCLKPOL = 1, as in Figure 48, the

latching edge of DACCLK is the rising edge of DACCLK that

occurs just before the rising edge of DATACLK. The setup

and hold time values are identical to those in Figure 44 and

Figure 45.

Note that there is a slight difference in the delay from the rising

edge of DACCLK to the falling edge of DATACLK, and the

delay from the rising edge of DACCLK to the rising edge of

DATACLK. As Figure 46 shows, the DATACLK duty cycle is

slightly less than 50%. This is true in all modes.

With the interpolation set to 4× or 8×, the DACCLK input runs

at 4× or 8× the speed of the DATACLK output. The data is

latched in on a rising edge of DACCLK, similar to the 2×

interpolation mode. However, the latching edge is every fourth

edge in 4× interpolation mode and every eighth edge in the 8×

interpolation mode. Similar to operation in the 2× interpolation

mode, with DCLKPOL = 0, the latching edge of DACCLK is the

rising edge that occurs just before the falling edge of

DATACLK. With DCLKPOL = 1, the latching edge of DACCLK

is the rising edge that occurs just before the rising edge of

DATACLK. The setup and hold time values are identical to

those in 1× and 2× interpolation.

Figure 46.

tD = 5ns TYP

tS = –0.5ns MIN

tH = 2.9ns MIN

DACCLKIN

DATACLKOUT

DATA

Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0

tD = 6ns TYP

tH = 2.9ns MIN

tS = –0.5ns MIN

DACCLKIN

DATACLKOUT

DATA

Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1

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