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CDCM1802RGTT датащи(PDF) 7 Page - Texas Instruments

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номер детали CDCM1802RGTT
подробное описание детали  CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output
PDF  30 Pages
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CDCM1802RGTT датащи(HTML) 7 Page - Texas Instruments

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CDCM1802
www.ti.com
SCAS759B – APRIL 2004 – REVISED NOVEMBER 2015
6.9 Control Input Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
Rpullup
Internal pullup resistor on S0, S1, and EN input
42
60
78
k
Ω
VIH(H)
Three level input high, S0, S1, and EN pin(1)
0.9 × VDD
V
VIM(M)
Three level input MID, S0, S1, and EN pin
0.3 × VDD
0.7 × VDD
V
VIL(L)
Three level low, S0, S1, and EN pin
0.1 × VDD
V
IIH
Input current, S0, S1, and EN pin
VI = VDD
–5
µA
IIL
Input current, S0, S1, and EN pin
VI = GND
38
85
µA
(1)
Leaving this pin floating automatically pulse the logic level high to VDD through an internal pullup resistor of 60 kΩ.
6.10 Timing Requirements
MIN
NOM
MAX
UNIT
tsu
Setup time, S0, S1, and EN pin before clock IN
25
ns
th
Hold time, S0, S1, and EN pin after clock IN
0
ns
Time between latching the EN low transition and when all outputs are
t(disable)
10
ns
disabled (how much time is required until the outputs turn off)
Time between latching the EN low-to-high transition and when outputs are
t(enable)
enabled based on control settings (how much time passes before the
1
μs
outputs carry valid signals)
6.11 Bias Voltage VBB
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBB
Output reference voltage
VDD = 3 V–3.6 V, IBB = –0.2 mA
VDD – 1.4
VDD – 1.2
V
Copyright © 2004–2015, Texas Instruments Incorporated
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Product Folder Links: CDCM1802



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