AD6635BB datasheet(38/60 Pages) AD

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AD6635

LINK PORT A CLOCK OUT

LINK PORT A CLOCK IN

LINK PORT A DATA

OR 8 LSBs OF

PARALLEL PORT A

DATA (SHARED PINS)

PCLKO

PARALLEL PORT A

MSB DATA

PARALLEL PORT A ACK

PARALLEL PORT A REQ

PARALLEL PORT A

I AND Q INDICATOR

PORT A

AD6635

ABOVE PINS SHARED

WITH PARALLEL PORT A

CHANNEL INDICATOR

Figure 34. Data Routing for Output Port A

Parallel port configuration is specified by accessing Port Control

mode (described later) is configured using the Port Clock Con-

trol register at address 0x1E. It should be noted that Output

Ports A and B have a separate clock (PCLK0) from Output

Ports C and D (PCLK1). Note that to access these registers,

Bit 5 (Access Port Control registers) of external address 3

(SLEEP register) must be set. The address is then selected by

programming the CAR register at external address 6.

The parallel ports are enabled by setting Bit 7 of the Link Con-

trol registers at addresses 0x1B and 0x1D.

Each parallel port is capable of operating in either Channel

mode or AGC mode. Each mode is described in detail below.

Channel Mode

Parallel port Channel mode is selected by setting Bit 0 of addresses

0x1A and 0x1B. In Channel mode, I and Q words from each

channel are directed to the parallel port, bypassing the interleaver,

the interpolating half-band filter, and AGC. The specific chan-

nels output by the port are selected by setting Bits 1–4 of the

Input Port Control register 0x1A and 0x1C. Each Channel

0–3 can be independently output on either Port A, Port B, or

both. Similarly, each Channel 4–7 can be independently output

on either Port C, Port D, or both.

Channel mode provides two data formats. Each format requires

a different number of parallel port clock (PCLK) cycles to com-

plete the transfer of data. In each case, each data element is

transferred during one PCLK cycle. See Figures 35 and 36,

which present Channel mode parallel port timing.

tDPCH

tDPIQ

tDPP

PCLKn

PxACK

PxREQ

tDPREQ

Px[15:0]

I[15:0]

Q[15:0]

PxlQ

PxCH[1:0]

PxCH[1:0] = CHANNEL NO.

Figure 35. Channel Mode Interleaved Format (16-bit I/Q)

tDPREQ

tDPCH

tDPIQ

tDPP

PCLKn

PxREQ

PxlQ

PxCH[1:0]

PxCH[1:0] =

CHANNEL NO.

Px[15:0]

I[15:8]; Q[7:0]

PxACK

Figure 36. Channel Mode 8I/8Q Parallel Format

The 16-bit interleaved format provides I and Q data for each

output sample on back-to-back PCLK cycles. Both I and Q

words consist of the full port width of 16 bits. Data output is

triggered on the rising edge of PCLK when both REQ and ACK

are asserted. I data is output during the first PCLK cycle, and

the PxIQ output indicator pins are set high to indicate that I

data is on the bus. Q data is output during the subsequent

PCLK cycle, and the PxIQ output indicator pins are low during

this cycle.

The 8-bit concurrent format provides 8 bits of I data and 8 bits

of Q data simultaneously during one PCLK cycle, also triggered

on the rising edge of PCLK. The I byte occupies the most sig-

nificant byte of the port, while the Q byte occupies the least

significant byte. The PxIQ (where x = A, B, C, or D) output

indicator pins are set high during the PCLK cycle. Note that if

data from multiple channels are output consecutively, the PxIQ

output indicator pins will remain high until data from all chan-

nels has been output. It should be noted that output Ports

(either parallel or link) A and B can output data only from

Channels 0–3, and similarly, Output Ports C and D can output

data only from Channels 4–7.

The PACH[1:0] and PBCH[1:0] pins provide a 2-bit binary

value indicating the source channel of the data currently being

output. This value will convey the channel numbers 0 to 3.

Similarly PCCH[1:0] and PDCH[1:0] pins provide a 2-bit

binary value indicating the source channel of the data currently

being output, the channels being 4 to 7. Binary value 00 indi-

cates Channel 4, and value 11 indicates Channel 7.

Care should be taken to read data from the port as soon as

possible. If not, the sample will be overwritten when the next

new data sample arrives. This occurs on a per channel basis;

i.e., a Channel 0 sample will only be overwritten by a new

Channel 0 sample, and so on.

The order of data output is dependent on when data arrived at

the port, which is a function of total decimation rate, Start

Holdoff values, and so on. Priority order is, from highest to

lowest, Channels 0, 1, 2, and 3, and similarly on Ports C and D

it is Channels 4, 5, 6, and 7.

AGC Mode

Parallel port channel mode is selected by clearing Bit 0 of

addresses 0x1A and 0x1C. I and Q data output in AGC mode

are output from the AGC, not the individual channels. Parallel

Ports A and B can provide data from either AGC A, AGC B, or

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