Preliminary Technical Data

AD5641

Rev. PrC | Page 13 of 20

DIN

DB15

DB16

DB0

DB0

INVALID WRITE SEQUENCE:

VALID WRITE SEQUENCE, OUTPUT UPDATES

SYNC

SCLK

Figure 27. SYNC Interrupt Facility

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 16 falling edges of SCLK and the DAC is updated on the

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 27).

POWER-ON RESET

The AD5641 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

zeros and the output voltage is 0 V. It remains there until a valid

write sequence is made to the DAC. This is useful in applica-

tions in which it is important to know the state of the DAC’s

output while it is in the process of powering up.

POWER-DOWN MODES

The AD5641 have four separate modes of operation. These

modes are software-programmable by setting two bits (DB15

and DB14) in the control register. Table 6 shows how the state of

the bits corresponds to the mode of operation of the device.

Table 6. Modes of Operation for the AD5641

DB15

DB14

Operating Mode

0

0

Normal operation

Power-down mode

0

1

1 kΩ to GND

1

0

100 kΩ to GND

1

1

Three-state

When both bits are set to 0, the part works normally with its

normal power consumption of 100 µA maximum at 5 V.

However, for the three power-down modes, the supply current

falls to <100 nA at 3 V. Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

options: the output is connected internally to GND through a

1 kΩ resistor or a 100 kΩ resistor, or the output is left open-

circuited (three-state). Figure 28 shows the output stage.

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

RESISTOR

STRING DAC

AMPLIFIER

Figure 28. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are all shut down when the power-

down mode is activated. However, the contents of the DAC

register are unaffected when in power-down. The time to exit

MICROPROCESSOR INTERFACING

AD5641 to ADSP-2101/ADSP-2103 Interface

Figure 29 shows a serial interface between the AD5641 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in SPORT transmit alternate framing mode.

The ADSP-2101/ADSP-2103 SPORT is programmed through

the SPORT control register and should be configured as follows:

internal clock operation, active low framing, and 16-bit word

length. Transmission is initiated by writing a word to the Tx

register after the SPORT has been enabled.



ADSP-2101/

ADSP-2103*

AD5641*

*ADDITIONAL PINS OMITTED FOR CLAIRTY

TFS

DT

SCLK

SYNC

DIN

SCLK

Figure 29. AD5641 to ADSP-2101/ADSP-2103 Interface