CD74FCT573, CD74FCT573AT

BiCMOS OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS744A – JULY 2000 – REVISED JULY 2000

3

POST OFFICE BOX 655303

recommended operating conditions (see Note 2)

MIN

MAX

UNIT

VCC

Supply voltage

4.75

5.25

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

VI

Input voltage

0

VCC

V

VO

Output voltage

0

VCC

V

IOH

High-level output current

–15

mA

IOL

Low-level output current

48

mA

∆t/∆v

Input transition rise or fall rate

0

10

ns/V

TA

Operating free-air temperature

0

70

°C

NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25°C

MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

MIN

MAX

UNIT

VIK

II = –18 mA

4.75 V

–1.2

–1.2

V

VOH

IOH = –15 mA

4.75 V

2.4

2.4

V

VOL

IOL = 48 mA

4.75 V

0.55

0.55

V

II

VI = VCC or GND

5.25 V

±0.1

±1

mA

IOZ

VO = VCC or GND

5.25 V

±0.5

±10

mA

IOS†

VI = VCC or GND,

VO = 0

5.25 V

–60

–60

mA

ICC

VI = VCC or GND,

IO = 0

5.25 V

8

80

mA

∆ICC‡

One input at 3.4 V,

Other inputs at VCC or GND

5.25 V

1.6

1.6

mA

Ci

VI = VCC or GND

10

10

pF

Co

VO = VCC or GND

15

15

pF

† Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.

‡ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.

timing requirements over recommended operating temperature conditions (unless otherwise

noted) (see Figure 1)

CD74FCT573

CD74FCT573AT

UNIT

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration

LE high

6

5

ns

tsu

Setup time

Data before LE

↓

2

2

ns

th

Hold time

Data after LE

↓

1.5

1.5

ns