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DAC7573IPWR датащи(PDF) 14 Page - Texas Instruments |
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DAC7573IPWR датащи(HTML) 14 Page - Texas Instruments |
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14 / 35 page ![]() www.ti.com DAC7573 I 2C Update Sequence Address Byte DAC7573 SLAS398 – SEPTEMBER 2003 The DAC7573 requires a start condition, a valid I 2C address, a control byte, an MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC7573 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I 2C address selects the DAC7573. The control byte sets the operational mode of the selected DAC7573. Once the operational mode is selected by the control byte, DAC7573 expects an MSB byte followed by an LSB byte for data update to occur. DAC7573 performs an update on the falling edge of the acknowledge signal that follows the LSB byte. The control byte needs not to be resent until a change in operational mode is required. The bits of the control byte continuously determine the type of update performed. Thus, for the first update, DAC7573 requires a start condition, a valid I 2C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates, DAC7573 needs an MSB byte, and an LSB byte as long as the control command remains the same. Using the I 2C high-speed mode (f scl= 3.4 MHz), the clock running at 3.4 MHz, each 12-bit DAC update other than the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge signal), at 188.88 KSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum DAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC7573 releases the I 2C bus and awaits a new start condition. MSB LSB 1 0 0 1 1 A1 A0 R/W The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select bits A1 and A0. The A1, A0 address inputs can be connected to VDD or digital GND, or can be actively driven by TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of the DAC7573. Up to 16 devices (DAC7573) can still be connected to the same I 2C-Bus. 14 |
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