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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMC7836IPAPR датащи(PDF) 69 Page - Texas Instruments |
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AMC7836IPAPR датащи(HTML) 69 Page - Texas Instruments |
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69 / 88 page  69 AMC7836 www.ti.com SLAS986C – NOVEMBER 2014 – REVISED APRIL 2016 Product Folder Links: AMC7836 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated 7.6.13.4 Power-Down 1 Register (address = 0xB3) [reset = 0x00] Figure 111. Power-Down 1 Register (R/W) 7 6 5 4 3 2 1 0 PDAC-D15 PDAC-D14 PDAC-D13 PDAC-D12 PDAC-C11 PDAC-C10 PDAC-C9 PDAC-C8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 60. Power-Down 1 Register Field Descriptions Bit Field Type Reset Description 7 PDAC-D15 R/W 0 After power-on or reset, all bits in the power-down register are cleared to 0, and all the components controlled by this register are either powered-down or off. The power-down register allows the host to manage the AMC7836 power dissipation. When not required, any of the DACs can be put into clamp mode and the ADC and internal reference into an inactive low-power mode to reduce current drain from the supply. The bits in the power-down register control this power-down function. Set the respective bit to 1 to activate the corresponding function. 6 PDAC-D14 R/W 0 5 PDAC-D13 R/W 0 4 PDAC-D12 R/W 0 3 PDAC-C11 R/W 0 2 PDAC-C10 R/W 0 1 PDAC-C9 R/W 0 0 PDAC-C8 R/W 0 7.6.13.5 Power-Down 2 Register (address = 0xB4) [reset = 0x00] Figure 112. Power-Down 2 Register (R/W) 7 6 5 4 3 2 1 0 Reserved PREF PADC R/W-All zeros R/W-0 R/W-0 Table 61. Power-Down 2 Register Field Descriptions Bit Field Type Reset Description 7-2 Reserved R/W All zeros Reserved for factory use. 1 PREF R/W 0 After power-on or reset, all bits in the power-down register are cleared to 0, and all the components controlled by this register are either powered-down or off. The power-down register allows the host to manage the AMC7836 power dissipation. When not required, any of the DACs can be put into clamp mode and the ADC and internal reference into an inactive low-power mode to reduce current drain from the supply. The bits in the power-down register control this power-down function. Set the respective bit to 1 to activate the corresponding function. 0 PADC R/W 0 |
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