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AM4376 датащи(PDF) 2 Page - Texas Instruments

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номер детали AM4376
подробное описание детали  AM437x Sitara Processors
PDF  266 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

AM4376 датащи(HTML) 2 Page - Texas Instruments

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AM4376, AM4377, AM4378, AM4379
SPRS851C – JUNE 2014 – REVISED APRIL 2016
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM4376 AM4377 AM4378 AM4379
Device Overview
Copyright © 2014–2016, Texas Instruments Incorporated
•
12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of
Instruction RAM With Single-Error Detection
(Parity)
•
8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of
Data RAM With Single-Error Detection
(Parity)
•
Single-Cycle 32-Bit Multiplier With 64-Bit
Accumulator
•
Enhanced GPIO Module Provides Shift-In
and Shift-Out Support and Parallel Latch on
External Signal
– 12KB (PRU-ICSS1 Only) of Shared RAM With
Single-Error Detection (Parity)
– Three 120-Byte Register Banks Accessible by
Each PRU
– Interrupt Controller Module (INTC) for Handling
System Input Events
– Local Interconnect Bus for Connecting Internal
and External Masters to the Resources Inside
the PRU-ICSS
– Peripherals Inside the PRU-ICSS
•
One UART Port With Flow Control Pins,
Supports up to 12 Mbps
•
One eCAP Module
•
Two MII Ethernet Ports that Support
Industrial Ethernet, such as EtherCAT
•
One MDIO Port
– Industrial Communication is Supported by Two
PRU-ICSS Subsystems
• Power, Reset, and Clock Management (PRCM)
Module
– Controls the Entry and Exit of Deep-Sleep
Modes
– Responsible for Sleep Sequencing, Power
Domain Switch-Off Sequencing, Wake-Up
Sequencing, and Power Domain Switch-On
Sequencing
– Clocks
•
Integrated High-Frequency Oscillator Used
to Generate a Reference Clock (19.2, 24, 25,
and 26 MHz) for Various System and
Peripheral Clocks
•
Supports Individual Clock Enable and
Disable Control for Subsystems and
Peripherals to Facilitate Reduced Power
Consumption
•
Five ADPLLs to Generate System Clocks
(MPU Subsystem, DDR Interface, USB, and
Peripherals [MMC and SD, UART, SPI, I2C],
L3, L4, Ethernet, GFX [SGX530], and LCD
Pixel Clock)
– Power
•
Two Nonswitchable Power Domains (RTC
and Wake-Up Logic [WAKE-UP])
•
Three Switchable Power Domains (MPU
Subsystem, SGX530 [GFX], Peripherals and
Infrastructure [PER])
•
Dynamic Voltage Frequency Scaling (DVFS)
• Real-Time Clock (RTC)
– Real-Time Date (Day, Month, Year, and Day of
Week) and Time (Hours, Minutes, and Seconds)
Information
– Internal 32.768-kHz Oscillator, RTC Logic, and
1.1-V Internal LDO
– Independent Power-On-Reset
(RTC_PWRONRSTn) Input
– Dedicated Input Pin (RTC_WAKEUP) for
External Wake Events
– Programmable Alarm Can Generate Internal
Interrupts to the PRCM for Wakeup or Cortex-
A9 for Event Notification
– Programmable Alarm Can Be Used With
External Output (RTC_PMIC_EN) to Enable the
Power-Management IC to Restore Non-RTC
Power Domains
• Peripherals
– Up to Two USB 2.0 High-Speed Dual-Role
(Host or Device) Ports With Integrated PHY
– Up to Two Industrial Gigabit Ethernet MACs
(10, 100, and 1000 Mbps)
•
Integrated Switch
•
Each MAC Supports MII, RMII, and RGMII
and MDIO Interfaces
•
Ethernet MACs and Switch Can Operate
Independent of Other Functions
•
IEEE 1588v2 Precision Time Protocol (PTP)
– Up to Two CAN Ports
•
Supports CAN Version 2 Parts A and B
– Up to Two Multichannel Audio Serial Ports
(McASPs)
•
Transmit and Receive Clocks up to 50 MHz
•
Up to Four Serial Data Pins Per McASP Port
With Independent TX and RX Clocks
•
Supports Time Division Multiplexing (TDM),
Inter-IC Sound (I2S), and Similar Formats
•
Supports Digital Audio Interface
Transmission (SPDIF, IEC60958-1, and
AES-3 Formats)
•
FIFO Buffers for Transmit and Receive
(256 Bytes)
– Up to Six UARTs
•
All UARTs Support IrDA and CIR Modes
•
All UARTs Support RTS and CTS Flow
Control
•
UART1 Supports Full Modem Control
– Up to Five Master and Slave McSPIs
•
McSPI0–McSPI2 Support up to Four Chip
Selects



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