DP8228 datasheet(3/6 Pages) NSC

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Capacitance VBIAS e 25V VCC e 50V TA e 25 C f e 1 MHz

Symbol

Parameter

Min

Typ

Max

Units

(Note 1)

CIN

Input Capacitance

COUT

Output Capacitance Control Signals

IO Capacitance (D or DB)

This parameter is periodically sampled and not 100% tested

Switching Characteristics Min s VCC s Max Min s TA s Max

DP8228M

DP8228

Symbol

Parameter

Conditions

DP8238M

DP8238

Units

Min

Max

Min

Max

tPW

Width of Status Strobe

tSS

Set-Up Time Status Inputs D0 – D7

tSH

Hold Time Status Inuts D0 – D7

tDC

Delay from STSTB to Any Control Signal

(Figure 2)

tRR

Delay from DBIN to Control Outputs

(Figure 2)

tRE

Delay from DBIN to Enable

(Figure 1)

Disable 8080 Bus

tRD

Delay from System Bus to 8080

(Figure 1)

Bus During Read

tWR

Delay from WR to Control Outputs

(Figure 2)

560545

tWE

Delay to Enable System Bus

(Figure 2)

DB0 – DB7 after STSTB

tWD

Delay from 8080 Bus D0 – D7 to

(Figure 2)

540540

System Bus DB0 – DB7 During Write

Delay from System Bus Enable to

(Figure 2)

System Bus DB0 – DB7

tHD

HLDA to Read Status Outputs

(Figure 2)

tDS

Set-Up Time System Bus Inputs to HLDA

tDH

Hold Time System Bus Inputs to HLDA

Test Conditions

TLF6825 – 2

TLF6825 – 3

TLF6825 – 4

FIGURE 1 Test Load

FIGURE 2 Test Load

FIGURE 3 INTA Test Circuit

(For RST 7)

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