ADS5400-SP

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SLAS669D – SEPTEMBER 2010 – REVISED JANUARY 2014

TIMING CHARACTERISTICS

(1)

(continued)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS/NOTES

MIN

TYP

MAX

UNIT

Clock period

1

10

ns

Clock pulse duration, high

Assuming worst case 45/55 duty cycle

0.45

ns

Clock pulse duration, low

Assuming worst case 55/45 duty cycle

0.45

ns

CLKIN rising to CLKOUT rising in divide by 2

1200

Clock propagation delay

ps

mode

CLKIN rising to CLKOUT rising in divide by 4

1200

Clock propagation delay

ps

mode

Bus A data propagation

1400

ps

delay

CLKIN falling to Data Output transition

Bus B data propagation

1400

ps

delay

Data valid to CLKOUT edge, 50% CLKIN duty

(3)

Setup time, single bus mode

290

ps

cycle

CLKOUT edge to Data invalid, 50% CLKIN duty

Hold time, single bus mode

410

ps

cycle

Data valid to CLKOUT edge, 50% CLKIN duty

Setup time, dual bus mode

550

ps

cycle

CLKOUT edge to Data invalid, 50% CLKIN duty

Hold time, dual bus mode

1150

ps

cycle

LVDS output rise time

400

ps

Measured 20% to 80%

LVDS output fall time

400

ps

LVDS INPUT TIMING (RESETIN)

RESET setup time

RESETP going HIGH to CLKINP going LOW

325

ps

RESET hold time

CLKINP going LOW to RESETP going LOW

325

ps

RESET input capacitance

Differential

1

pF

RESET input current

±1

µA

SERIAL INTERFACE TIMING

Setup time, serial enable

SDENB falling to SCLK rising

20

ns

Hold time, serial enable

SCLK falling to SENDB rising

25

ns

Setup time, SDIO

SDIO valid to SCLK rising

10

ns

Hold time, SDIO

SCLK rising to SDIO transition

10

ns

Frequency

10

MHz

SCLK period

100

ns

Minimum SCLK high time

40

ns

Minimum SCLK low time

40

ns

Rise time

10pF

10

ns

Fall time

10pF

10

ns

Data output (SDO/SDIO) delay after SCLK

Data output delay

75

ns

falling, 10pF load

(2)

LVDS output timing measured with a differential 100

Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance

is 3.5pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5pF differential. All timing

parameters are relative to the device pins, with the loading as stated.

(3)

In single bus mode at 1GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum

700ps of data valid window, with 300ps of uncertainity.

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7

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