TMS320VC5416 datasheet(78/98 Pages) TI

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5.5.10

Multichannel Buffered Serial Port (McBSP) Timing

5.5.10.1

McBSP Transmit and Receive Timings

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Table 5-20 and Table 5-21 assume testing over recommended operating conditions (see Figure 5-21 and

Figure 5-22).

Table 5-20. McBSP Transmit and Receive Timing Requirements

(1)

5416-120

5416-160

UNIT

MIN

MAX

tc(BCKRX)

Cycle time, BCLKR/X(2)

BCLKR/X ext

4P(3)

tw(BCKRX)

Pulse duration, BCLKR/X high or BCLKR/X low(2)

BCLKR/X ext

2P–1(3)

BCLKR int

tsu(BFRH-BCKRL)

Setup time, external BFSR high before BCLKR low

BCLKR ext

BCLKR int

th(BCKRL-BFRH)

Hold time, external BFSR high after BCLKR low

BCLKR ext

BCLKR int

tsu(BDRV-BCKRL)

Setup time, BDR valid before BCLKR low

BCLKR ext

BCLKR int

th(BCKRL-BDRV)

Hold time, BDR valid after BCLKR low

BCLKR ext

BCLKX int

tsu(BFXH-BCKXL)

Setup time, external BFSX high before BCLKX low

BCLKX ext

BCLKX int

th(BCKXL-BFXH)

Hold time, external BFSX high after BCLKX low

BCLKX ext

tr(BCKRX)

Rise time, BCKR/X

BCLKR/X ext

tf(BCKRX)

Fall time, BCKR/X

BCLKR/X ext

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If the polaritiy of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be

achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A

separate detailed timing analysis should be performend for each specific McBSP interface.

(3)

P = 0.5 * processor clock.

Electrical Specifications

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