Minimizing Settling Time

The DAC0890’s output stage uses a passive pull-down re-

sistor to achieve single supply operation and an output volt-

age range that includes ground This results in a negative-

going settling time that is longer than the settling time or

positive-going signals The actual settling time is dependant

on the load resistance and capacitance If available a nega-

tive power supply can be used to improve the negative set-

tling time by connecting a pull down resistor between the

output and the negative supply The resistor’s value is cho-

sen so that the current through the pull down resistor is not

greater than 05 mA when the output voltage is 0V See

Figure 4

TLH10592 – 11

FIGURE 4 Improving Negative Slew Rate

Bipolar Operation

While the DAC0890 was designed to operate on a single

positive supply voltage and generate a unipolar output volt-

age bipolar operation is still possible if a negative supply is

available or added As shown in

Figure 5 the output voltage

is generated with an LM385 – 12V reference The external

output amplification is provided by the LMC660 The output

voltage is generated with a complementary binary offset in-

put code

Microprocessor Interface

When interfacing with a microprocessor the DAC0890 ap-

pears as a two byte write-only memory location for memory

mapped and IO mapped input-output Each of the internal

DACs is chosen through one of the two chips selects CS1

or CS2 The action of the control signals is detailed in Table

I The data is latched on the rising edge of either Chip Se-

lect or WR whichever occurs first for a given selected DAC

For interfacing ease WR can be tied low and CS1 or CS2

can be used to latch the data Both DACs can be updated

simultaneously by pulling both CS1 and CS2 low Further

versatility is provided by the ability of WR and CS1 andor

CS2 to be tied together

TABLE I DAC0890 Control Logic Truth Table

Input

WR

CS

DAC Data

Latch

Data

Condition

0

0

0

0

‘‘transparent’’

1

0

0

1

‘‘transparent’’

0

u

0

0

latching

1

u

0

1

latching

00

u

0

latching

10

u

1

latching

X

1

X

previous data

latching

X

X

1

previous data

latching

X

1

1

previous data

latching

TLH10592 – 12

FIGURE 5 Bipolar Operation

10