FT810Q datasheet(27/60 Pages) FTDI

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Document No.: FT_001165

FT81X

Embedded Video Engine

Datasheet Version 1.2

Clearance No.:

FTDI#440

REG_PCLK

System Clock Frequency (MHz)

60(default)

7.5

6.0

4.5

3.0

6.7

5.3

4.0

2.7

6.0

4.8

3.6

2.4

REG_PCLK_POL defines the clock polarity, with 0 for positive active clock edge, and 1 for negative clock

edge.

REG_CSPREAD controls the transition of RGB signals with respect to the PCLK active clock edge. When

REG_CSPREAD=0, R[7:0], G[7:0] and B[7:0] signals change following the active edge of PCLK. When

REG_CSPREAD=1, R[7:0] changes a PCLK clock early and B[7:0] a PCLK clock later, which helps reduce

the switching noise.

REG_DITHER enables colour dither. This option improves the half-tone appearance on displays.

Internally, the graphics engine computes the colour values at an 8 bit precision; however, the LCD colour

at a lower precision is sufficient. The FT810/FT811 output is only 6 bits per colour in 6:6:6 formats and a

2X2 dither matrix allow the truncated bits to contribute to the final colour values.

REG_OUTBITS gives the bit width of each colour channel, the default is 6/6/6(for FT810/FT811) or

8/8/8(for FT812/FT813) bits for each R/G/B colour. A lower value means fewer bits are output for each

channel allowing dithering on lower precision LCD displays.

REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route different LCD

panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be reversed.

Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped. Setting Bit 3 allows

rotation to be enabled. If Bit 3 is set, then (R,G,B) is rotated right if bit 2 is one, or left if bit 2 is zero.

Table 4-12 REG_SWIZZLE RGB Pins Mapping

REG_SWIZZLE

PINS (FT810/FT811, 6 bits)

PINS (FT812/FT813, 8 bits)

b3 b2 b1 b0 R7, R6, R5,

R4, R3, R2

G7, G6, G5,

G4, G3, G2

B7, B6, B5,

B4, B3, B2

R7, R6,

R5, R4,

R3, R2,

R1, R0

G7, G6,

G5, G4,

G3, G2,

G1, G0

B7, B6,

B5, B4,

B3, B2,

B1, B0

R[7:2]

G[7:2]

B[7:2]

R[7:0]

G[7:0]

B[7:0]

R[2:7]

G[2:7]

B[2:7]

R[0:7]

G[0:7]

B[0:7]

B[7:2]

G[7:2]

R[7:2]

B[7:0]

G[7:0]

R[7:0]

B[2:7]

G[2:7]

R[2:7]

B[0:7]

G[0:7]

R[0:7]

B[7:2]

R[7:2]

G[7:2]

B[7:0]

R[7:0]

G[7:0]

B[2:7]

R[2:7]

G[2:7]

B[0:7]

R[0:7]

G[0:7]

G[7:2]

R[7:2]

B[7:2]

G[7:0]

R[7:0]

B[7:0]

G[2:7]

R[2:7]

B[2:7]

G[0:7]

R[0:7]

B[0:7]

G[7:2]

B[7:2]

R[7:2]

G[7:0]

B[7:0]

R[7:0]

G[2:7]

B[2:7]

R[2:7]

G[0:7]

B[0:7]

R[0:7]

R[7:2]

B[7:2]

G[7:2]

R[7:0]

B[7:0]

G[7:0]

R[2:7]

B[2:7]

G[2:7]

R[0:7]

B[0:7]

G[0:7]

REG_HCYCLE, REG_HSIZE, REG_HOFFSET, REG_HSYNC0 and REG_HSYNC1 define the LCD horizontal

timings. Each register has 12 bits to allow programmable range of 0-4095 PCLK cycles. REG_VCYCLE,

REG_VSIZE, REG_VOFFSET, REG_VSYNC0 and REG_VSYNC1 define the LCD vertical timings. Each

Table 4-13 Registers for RGB horizontal and vertical timings

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