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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MB9B360R датащи(PDF) 82 Page - Cypress Semiconductor |
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MB9B360R датащи(HTML) 82 Page - Cypress Semiconductor |
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82 / 166 page  Document Number: 002-04872 Rev.*A Page 82 of 166 MB9B360R Series 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* 1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency FPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency FPLLO 200 - 320 MHz Main PLL clock frequency* 2 FCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CL KPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”. 12.4.5 Operating Conditions of USB PLL (In the case of using main clock for input clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* 1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency FPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency FPLLO 200 - 320 MHz USB clock frequency* 2 FCLKSPLL - - 48 MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about USB clock, see "Chapter: USB Clock Generation" in "FM4 Family Peripheral Manual Communication Macro Part". 12.4.6 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* 1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency FPLLI 3.8 4 4.2 MHz PLL multiplication rate - 50 - 75 multiplier PLL macro oscillation clock frequency FPLLO 190 - 320 MHz Main PLL clock frequency* 2 FCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CL KPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”. Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed. |
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