MAC7100 datasheet(18/48 Pages) MOTOROLA

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MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Electrical Characteristics

3.8.6

Startup

Table 21 summarizes several startup characteristics explained in this section. Refer to the MAC7100

Microcontroller Family Reference Manual (MAC7100RM/D) for a detailed description of the startup

behavior.

3.8.6.1

Power On and Low Voltage Reset (POR and LVR)

The release level VPORR and the assert level VPORA are derived from the VDD2.5 supply. The assert level

VLVRA is derived from the VDD2.5 supply. They are also valid if the device is powered externally. After

releasing the POR or LVR reset, the oscillator and the clock quality check are started. If after a time tCQOUT

no valid oscillation is detected, the MCU will start using the internal self-generated clock. The fastest startup

time possible is given by tuposc (refer to Table 17).

3.8.6.2

SRAM Data Retention

The SRAM contents integrity is guaranteed if the PORF bit in the CRGFLG register is not set following a

reset operation.

3.8.6.3

External Reset

When external reset is asserted for a time greater than PWRSTL, the CRG module generates an internal reset

and the CPU starts fetching the reset vector without doing a clock quality check, if there was stable

oscillation before reset.

3.8.6.4

Stop Recovery

The MCU can be returned to run mode from the stop mode by an external interrupt. A clock quality check

is performed in the same manner as for POR before releasing the clocks to the system.

3.8.6.5

Pseudo Stop and Doze Recovery

Recovery from pseudo stop and doze modes are essentially the same, since the oscillator is not stopped in

either mode. The controller is returned to run mode by internal or external interrupts or other wakeup events

in the system. After twrs, the CPU fetches an interrupt vector if the wakeup event was an interrupt, or

continues to execute code if the wakeup event was not an interrupt.

Table 21. CRG Startup Characteristics

Num C

Rating

Symbol

Min

Typ

Max

Unit

T POR release level

VPORR

——

2.07

T POR assert level

VPORA

0.97

—

D Reset input pulse width, minimum input time

PWRSTL

2—

—

tosc

D Startup from Reset

nRST

192

—

196

nosc

D Interrupt pulse width, IRQ edge-sensitive mode

PWIRQ

—

D Wait recovery startup time

tWRS

——

tcyc

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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