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LTC3206EUF датащи(PDF) 3 Page - Linear Technology |
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LTC3206EUF датащи(HTML) 3 Page - Linear Technology |
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3 / 16 page ![]() LTC3206 3 3206f ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V unless otherwise noted. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3206E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: 1.5x mode output impedance is defined as (1.5VIN – VCPO)/IOUT. Note 4: Based on long term current density limitations. Note 5: All values are referenced to VIH and VIL levels. TYPICAL PERFOR A CE CHARACTERISTICS LED Pin Dropout Voltage vs LED Pin Current LED Pin Sink Current vs LED Pin Voltage ILED 2.5mA/DIV CPO AC COUPLED (50mV/DIV) VIN AC COUPLED (50mV/DIV) Input and Output Charge Pump Noise 200mV/DIV 3206 G01 ICPO = 200mA 500ns/DIV 3206 G02 VIN = 3.6V CIN = CCPO = 1.6µF 0mA LED CURRENT (mA) 100 0 100 300 400 500 20 40 50 90 3206 GO3 200 10 30 60 70 80 VIN = 3.6V TA = 25°C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CPO Regulation Voltage ICPO = 20mA, 1.5x Mode 4.75 V CLK Frequency 0.68 0.96 1.36 MHz SDA, SCL, ENRGB/S VIL Low Level Input Voltage ● 0.3 • DVCC V VIH High Level Input Voltage ● 0.7 • DVCC V IIH Input Current SDA, SCL, ENRGB/S = DVCC –1 1 µA IIL Input Current SDA, SCL, ENRGB/S = 0V –1 1 µA VOL Digital Output Low (SDA) IPULLUP = 3mA ● 0.4 V Timing Characteristics (Note 5) tSCL Clock Operating Frequency 400 kHz tBUF Bus Free Time Between Stop and Start Condition 1.3 µs tHD, STA Hold Time After (Repeated) Start Condition 0.6 µs tSU, STA Repeated Start Condition Setup Time 0.6 µs tSU, STD Stop Condition Setup Time 0.6 µs tHD, DAT(OUT) Data Hold Time 225 900 ns tHD, DAT(IN) Input Data Hold Time 0 900 ns tSU, DAT Data Setup Time 100 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs tf Clock Data Fall Time 20 300 ns tr Clock Data RiseTime 20 300 ns tSP Spike Suppression Time 50 ns VLED AT CURRENT SOURCE PIN 25% 50% 100% |
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