PRELIMINARY

DS2432

26 of 30

Read/Write Time Slots

The definitions of write and read time slots are illustrated in Figure 11. The master initiates all time slots

by driving the data line low. The falling edge of the data line synchronizes the DS2432 to the master by

triggering an internal delay circuit. During write time slots, the delay circuit determines when the DS2432

will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS2432 will hold the data line low. If the data bit is a “1”, the DS2432 will not

hold the data line low at all.

READ/WRITE TIMING DIAGRAM Figure 11

Write-one Time Slot

0V

15 µs

(OD: 2 µs)

60 µs

(OD: 6 µs)

DS2432

Sampling Window

REGULAR SPEED

60 µs

≤ t

1 µs

≤ t

1 µs

≤ t

∞

OVERDRIVE SPEED

6 µs

≤ t

1 µs

≤ t

1 µs

≤ t

∞

RESISTOR

MASTER

Write-zero Time Slot

0V

REGULAR SPEED

60 µs

≤ t

1 µs

≤ t

∞

OVERDRIVE SPEED

6 µs

≤ t

1 µs

≤ t

∞

RESISTOR

MASTER

15 µs

(OD: 2 µs)

60 µs

(OD: 6 µs)

DS2432

Sampling Window