A resistive divider made from the 143

Ω and 60.4Ω resistors

was chosen to reduce the loop-gain and stabilize the net-

work. The CLC5802 composite integrator provides integra-

tion over five decades of operation. R and C set the integra-

tor’s gain.

Figure 4 shows the frequency and phase

response of the circuit in

Figure 3 with R = 44.2

Ω and C =

360pF.

K: R2/(R1 + R2)

A

Positive Peak Detector

The CLC5802’s dual amplifiers can be used to implement a

unity-gain peak detector circuit as shown in

Figure 5.

The acquisition speed of this circuit is limited by the dynamic

resistance of the diode when charging C

cuit’s performance is shown in

Figure 6 with a 1MHz sinusoi-

dal input.

A current source, built around Q1, provides the necessary

bias current for the second amplifier and prevents saturation

when power is applied. The resistor, R, closes the loop while

diode D

V

capacitor’s voltage.

The maximum speed of detection is limited by the delay of

the op amp and the diodes. The use of Schottky diodes will

provide faster response.

Adjustable or Bandpass Equalizer

A “boost” equalizer can be made with the CLC5802 by sum-

ming a bandpass response with the input signal, as shown in

Figure 7.

The overall transfer function is shown in

Equation (3).

(3)

To build a boost circuit, use the design Equation 4 and 5.

(4)

(5)

Select R

for high frequency circuits - R

tween 10pF and 2000pF. Use

Equation (5) to determine the

parallel combination of R

ther the 10

Ω to 5kΩ criteria or by other requirements based

on the impedance V

by determining the value of K from

Equation (6).

DS101341-29

FIGURE 4.

DS101341-30

FIGURE 5.

DS101341-31

FIGURE 6.

DS101341-32

FIGURE 7.

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