CLC5632 datasheet(12/19 Pages) NSC

12 / 19 page

Application Division (Continued)

•

Z(j

ω)/R

f is the loop gain

The denominator of Equation 1 is approximately equal to 1 at

low frequencies. Near the −3dB corner frequency, the inter-

action between R

f and Z(jω) dominates the circuit perfor-

mance. The value of the feedback resistor has a large affect

on the circuits performance. Increasing R

f has the following

affects:

•

Decreases loop gain

•

Decreases bandwidth

•

Reduces gain peaking

•

Lowers pulse response overshoot

•

Affects frequency response phase linearity

CLC5632 Design Information

Closed Loop Gain Selection

The CLC5632 is a current feedback op amp with R

f =Rg =

Ω on chip (in the package). Select from three closed loop

gains without using any external gain or feedback resistors.

Implement gains of +2, +1, and −1V/V by connecting pins 2

and 3 (or 5 and 6) as described in the chart below.

Gain A

Input Connections

Non-Inverting (pins 3, 5)

Inverting (pins 2, 6)

−1V/V

ground

input signal

+1V/V

input signal

NC (open)

+2V/V

input signal

ground

The gain accuracy of the CLC5632 is excellent and stable

over temperature change. The internal gain setting resistors,

f and Rg are diffused silicon resistors with a process varia-

tion of ± 20% and a temperature coefficient of - 2000ppm/˚C.

Although their absolute values change with processing and

temperature, their ratio (R

f/Rg) remains constant. If an exter-

nal resistor is used in series with R

g, gain accuracy over

temperature will suffer.

Single Supply Operation (V

CC = +5V, VEE = GND)

The specifications given in the +5V Electrical Characteris-

tics table for single supply operation are measured with a

common mode voltage (V

CM) of 2.5V. VCM is the voltage

around which the inputs are applied and the output voltages

are specified.

Operating from a single +5V supply, the Common Mode

Input Range (CMIR) of the CLC5632 is typically +0.8V to

+4.2V. The typical output range with R

L = 100Ω is +1.0V to

+4.0V.

For single supply DC coupled operation, keep input signal

levels above 0.8V DC, AC coupling and level shifting the

signal are recommended. The non-inverting and inverting

configurations for both input conditions are illustrated in the

following 2 sections.

DC Coupled Single Supply Operation

Figure 1, Figure 2, and Figure 3 on the following page, show

the recommended configurations for input signals that re-

main above 0.8V DC.

DS015003-39

FIGURE 1. DC Coupled, A

V = −1V/V Configuration

Ω

CLC5632

Vcm

0.1

µF

6.8

µF

Vin

Vcm

VCC

Note: Rt and RL are tied to Vcm for minimum power

consumption and maximum output swing.

Channel 2 not shown.

DS015003-40

FIGURE 2. DC Coupled, A

V = +1V/V Configuration

Ω

CLC5632

Vcm

0.1

µF

6.8

µF

Vin

Vcm

VCC

Note: Rt, RL and Rg are tied to Vcm for minimum power

consumption and maximum output swing.

Channel 2 not shown.

Vcm

DS015003-41

FIGURE 3. DC Coupled, A

V = +2V/V Configuration

CLC5632 датащи(PDF) 12 Page - National Semiconductor (TI)

CLC5632 датащи(HTML) 12 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

датащи скачать

ссылки URL