Layout Considerations

A proper printed circuit layout is essential for achieving high

frequency performance. National provides evaluation boards

for the CLC5612 (CLC730038-DIP, CLC730036-SOIC) and

suggests their use as a guide for high frequency layout and

as an aid for device testing and characterization.

General layout and supply bypassing play major roles in high

frequency performance. Follow the steps below as a basis

for high frequency layout:

•

Include 6.8µF tantalum and 0.1µF ceramic capacitors on

both supplies.

•

Place the 6.8µF capacitors within 0.75 inches of the

power pins.

•

Place the 0.1µF capacitors less than 0.1 inches from the

power pins.

•

Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance.

•

Minimize all trace lengths to reduce series inductances.

•

Use flush-mount printed circuit board pins for prototyping,

never use high profile DIP sockets.

Evaluation Board Information

A data sheet is available for the CLC730038/CLC730036

evaluation boards. The evaluation board data sheets

provide:

•

Evaluation board schematics

•

Evaluation board layouts

•

General information about the boards

The evaluation boards are designed to accommodate dual

supplies. The boards can be modified to provide dual

supplies. The boards can be modified to provide single

supply operation. For best performance; 1) do not connect

the unused supply, 2) ground the unused supply pin.

Special

Evaluation

Board

Considerations

for

the

CLC5612

To optimize off-isolation of the CLC5612, cut the R

both the CLC730038 and the CLC730036 evaluation

boards. This cut minimizes capacitive feedthrough between

the input and the ouptut.

Figure 13 shows where to cut both

evaluation boards for improved off-isolation.

SPICE Models

SPICE models provide a means to evaluate amplifier

designs. Free SPICE models are available for National’s

monolithic amplifiers that:

•

Support Berkeley SPICE 2G and its many deriatives

•

Reproduce typical DC, AC, Transient, and Noise

performance

•

Support room temperature simulations

The readme file that accompanies the diskette lists released

models and provides a list of modeled parameters. The

application note OA-18, Simulation SPICE Models for

National’s

Op

Amps,

contains

schematics

and

a

reproduction of the readme file.

DS015001-61

OUT2

GND

IN2

IN1

OUT1

+Vcc

-Vcc

ROUT2

RG2

RF2

C3

+

C4

+

C1

C2

ROUT1

RF1

RG1 RIN1

RIN2

(970) 226-0500

Cut traces here

730036 Top

DS015001-52

FIGURE 13. Evaluation Board Changes

www.national.com

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