O

O

O

O

Operation

The CLC532 is a 2:1 analog multiplexer with high-impedance

buffered inputs, and a low-impedance, low-distortion, output

stage.

The CLC532 employs a closed-loop design, which

dramatically improves accuracy. The channel SELECT control

(Figure 1) determines which of the two inputs (IN

present at the OUTPUT. Beyond the basic multiplexer function,

the CLC532 offers compatibility with either TTL or ECL logic

families, as well as adjustable bandwidth.

5

8

10

6

9

4

3

2

1

7

13

14

12

CHANNEL A

CHANNEL B

CHANNEL

SELECT

DGND

-5.2V

0.1

µF

2

1

+5V

CLC532

11

0.1

µF

+6.8

µF

+6.8

µF

Figure 1: Standard CLC532 Circuit Configuration

Digital Interface and Channel SELECT

The CLC532 functions with ECL, TTL and CMOS logic families.

D

floating, and the channel SELECT responds to ECL level signals,

Figure 2. For TTL or CMOS level SELECT inputs (Figure 3), D

REF

should be tied to +5V (the CLC532 incorporates an internal

2300

Ω series isolation resistor for the D

For TTL or

CMOS operation, the channel SELECT requires a resistor input

network to prevent saturation of the channel select circuitry.

Without this input network, channel SELECT logic levels above

3V will cause internal junction saturation and slow switching

speeds.

ECL GATE

CHANNEL

SELECT

A

50

Ω

50

Ω

-2V

7

SELECT

6

(NC)

CLC532

-5.2V

To ECL

Gate

To

SELECT

130

Ω

81

Ω

Thevinen Equivalent

Output Termination

R1

R2

Figure 2: ECL Level Channel SELECT Configuration

+5V

CHANNEL

SELECT

A

7

6

+5V

CLC532

TTL

CMOS

R3

R2

R1

Ω

Ω

Ω

Ω

Ω

Ω

620

200

510

3.6k

510

680

R2

R3

R1

Figure 3: TTL/CMOS Level Channel SELECT Configuration

Compensation

The CLC532 incorporates compensation nodes that allow both

its bandwidth and its settling time/slew rate to be adjusted.

Bandwidth and settling time/slew adjustments are linked,

meaning that lowering the bandwidth also lowers slew rate

and lengthens settling time. Proper adjustment (compensation)

is necessary to optimize system performance. Time Domain

applications should generally be optimized for lowest

RMS

noise at the CLC532 output, while maintaining settling time and

slew rates at adequate levels to meet system needs. Frequency

Domain applications should generally be optimized for maximally

flat frequency response.

Figure 4

below describes the basic relationship between

bandwidth and R

where C

0.01%

0.05%

Rs

Ts

1k

Ω

C

L

2V Output Step

1

100

1000

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

Figure 4: Settling Time and R

Figure 5 shows the resulting changes in bandwidth and slew rate

for increasing values of C

output can be approximated as:

OUTPUT

where... n

BW

1

10

100

200

180

160

140

120

100

80

60

40

20

0

-3dB Bandwidth

Slew Rate

200

180

160

140

120

100

80

60

40

20

Figure 5: C

Applications Information

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