GMS30C7201 datasheet(89/352 Pages) HYNIX

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SDRAM Controller

8-17

GMS30C7201 Data Sheet

8.8

Merging Write Buffer

An eight word merging write buffer is implemented in the SDRAM controller to improve write

performance. The write buffer can be disabled, but its operation is completely transparent to the

programmer. The eight words of the buffer are split into two quad words, the same size as all

data transactions to the SDRAMs. The split into two quad words allows one quad word to be

written to at the same time as the contents of the other are being transferred to SDRAM. The

quad word buffer currently being written to may be accessed with non-contiguous word, half

word or byte writes, which will be merged into a single quad word. The buffered quad word will

be transferred to the SDRAM when:

•

there is a write to an SDRAM address outside the current quad word being merged into

•

there is a read to the address of the quad word being merged into

•

there is a time-out on the write back timer

The two quad-words that make up the write buffer operate in “ping-pong” fashion, whereby one

is initially designated the buffer for writes to go into, and the other is the buffer for write backs.

When one of the three events that can cause a write-back occurs, the functions of the two buffers

are swapped. Thus the buffer containing data to be written back becomes the buffer that is

currently writing back, and the buffer that was the write-back buffer becomes the buffer being

written to.

In the case of a write-back initiated by a read from the same address as the data in the merge

buffer, the quad word in the buffer is written to SDRAM, and then the read occurs from

SDRAM. The write before read is essential, because not all of the quad word in the buffer may

have been updated, so its contents need to be merged with the SDRAM contents to fill any gaps

where the buffer was not updated.

The write buffer flush timer forces a write back to occur after a programmable amount of time.

Every time a write into the buffer occurs, the counter is re-loaded with the programmed time-

out value, and starts to counts down. If a time-out occurs, then data in the write buffer is written

to SDRAM.

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