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DSP56362AD датащи(PDF) 49 Page - Motorola, Inc

номер детали DSP56362AD
подробное описание детали  24-Bit Audio Digital Signal Processor
PDF  168 Pages
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производитель  MOTOROLA [Motorola, Inc]
домашняя страница  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

DSP56362AD датащи(HTML) 49 Page - Motorola, Inc

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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
MOTOROLA
DSP56362 Advance Information
2-11
25
Delay from IRQA assertion to
fetch of first instruction (when
exiting Stop)2, 3
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop
delay is enabled
(OMR Bit 6 = 0)
PLC
× ETC × PDF +
(128 K
− PLC/2) × TC
1.3
13.6
—
—
ms
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR
Bit 6 = 1)
PLC
× ETC × PDF +
(23.75
± 0.5) × TC
232.5
ns
12.3 ms
—
—
• PLL is active during Stop
(PCTL Bit 17 = 1) (Implies
No Stop Delay)
(8.25
± 0.5) × TC
77.5
87.5
64.6
72.9
ns
26
Duration of level sensitive IRQA
assertion to ensure interrupt
service (when exiting Stop)2, 3
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop
delay is enabled
(OMR Bit 6 = 0)
PLC
× ETC × PDF +
(128K
− PLC/2) × TC
13.6
—
ms
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop
delay is not enabled
(OMR Bit 6 = 1)
PLC
× ETC × PDF +
(20.5
± 0.5) × TC
12.3
—
ms
• PLL is active during Stop
(PCTL Bit 17 = 1) (implies no
Stop delay)
5.5
× TC
55.0
—
45.8
—
ns
27
Interrupt Requests Rate
• HI08, ESAI, SHI, Timer
12TC
—
120.0
—
100.0
ns
•DMA
8TC
—
80.0
—
66.7
ns
•IRQ, NMI (edge trigger)
8TC
—
80.0
—
66.7
ns
•IRQ, NMI (level trigger)
12TC
—
120.0
—
100.0
ns
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values6
No.
Characteristics
Expression
100 MHz
120 MHz
Unit
Min
Max
Min
Max
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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