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CLC450 датащи(PDF) 9 Page - National Semiconductor (TI) |
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CLC450 датащи(HTML) 9 Page - National Semiconductor (TI) |
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9 / 12 page ![]() 9 http://www.national.com Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 7 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Figure 7: Transmission Line Matching Non-inverting gain applications: s Connect Rg directly to ground. s Make R1, R2, R6, and R7 equal to Zo. s Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Inverting gain applications: s Connect R3 directly to ground. s Make the resistors R4, R6, and R7 equal to Zo. s Make R5 II Rg = Zo. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. Power Dissipation Follow these steps to determine the power consumption of the CLC450: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po The maximum power that the DIP, SOIC, and SOT packages can dissipate at a given temperature is illustrated in Figure 8. The power derating curve for any CLC450 package can be derived by utilizing the following equation: where Tamb = Ambient temperature (°C) θ JA = Thermal resistance, from junction to ambient, for a given package (°C/W) Figure 8: Power Derating Curves Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC450 (730013-DIP, 730027- SOIC, 730068-SOT) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: s Include 6.8 µF tantalum and 0.1µF ceramic capacitors on both supplies. s Place the 6.8 µF capacitors within 0.75 inches of the power pins. s Place the 0.1 µF capacitors less than 0.1 inches from the power pins. s Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. s Minimize all trace lengths to reduce series inductances. s Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information Data sheets are available for the CLC730013/ CLC730027 and CLC730068 evaluation boards. The evaluation board data sheets provide: s Evaluation board schematics s Evaluation board layouts s General information about the boards The CLC730013/CLC730027 data sheet also contains tables of recommended components to evaluate several of National’s high speed amplifiers. This table for the CLC450 is illustrated below. Refer to the evaluation board data sheet for schematics and further information. Components Needed to Evaluate the CLC450 on the Evaluation Board: s Rf, Rg - Use this product data sheet to select values s Rin, Rout - Typically 50Ω (Refer to the Basic Operation section of the evaluation board data sheet for details) (175 Tamb JA °− ) θ Ambient Temperature ( °C) 0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 180 AJP AJE SOT 140 160 CLC450 + - R3 Z0 R6 Vo Z0 R1 R2 + - Rg Z0 R4 R5 V1 V2 +- Rf C6 R7 |
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