RT4813 datasheet(15/16 Pages) RICHTEK

15 / 16 page

RT4813

is a registered trademark of Richtek Technology Corporation.

DS4813-00

April

2016

www.richtek.com

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature.

The maximum power dissipation can be calculated by

the following formula :

PD(MAX) = (TJ(MAX)  TA) / JA

where TJ(MAX) is the maximum junction temperature,

TA is the ambient temperature, and JA is the junction to

ambient thermal resistance.

For recommended operating condition specifications,

the maximum junction temperature is 125

C. The

junction to ambient thermal resistance,

JA, is layout

dependent. For UQFN-9L 2x2 (FC) package, the

thermal resistance,

JA, is 111.5C/W on a standard

JEDEC 51-7 four-layer thermal test board. The

maximum power dissipation at TA = 25C can be

calculated by the following formula :

PD(MAX) = (125C  25C) / (111.5C/W) = 0.89W for

UQFN-9L 2x2 (FC) package

The maximum power dissipation depends on the

operating ambient temperature for fixed TJ(MAX) and

thermal resistance,

JA. The derating curve in Figure 3

allows the designer to see the effect of rising ambient

temperature on the maximum power dissipation.

Figure 3. Derating Curve of Maximum Power

Dissipation

Layout Consideration

The PCB layout is an important step to maintain the

high performance of RT4813.

Both the high current and the fast switching nodes

demand full attention to the PCB layout to save the

robustness of the RT4813 through the PCB layout.

Improper layout might show the symptoms of poor line

or load regulation, ground and output voltage shifts,

stability issues, unsatisfying EMI behavior or worsened

efficiency. For the best performance of the RT4813, the

following PCB layout guidelines must be strictly

followed.



Input/Output capacitors must be placed as close as

possible to the Input/Output pins.



SW should be connected to Inductor by wide and

short trace, keep sensitive components away from

this trace.



The feedback divider should be placed as close as

possible to the FB pin.

Vin

Vout

GND

Cout

Figure 4. PCB Layout Guide

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

RT4813 датащи(PDF) 15 Page - Richtek Technology Corporation

RT4813 датащи(HTML) 15 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

датащи скачать

ссылки URL